TheCortex-M3processorPM0056Program status registerTheProgramStatusRegister(PSR)combines:ApplicationProgramStatusRegister(APSR)InterruptProgramStatusRegister(IPSR)ExecutionProgramStatusRegister(EPSR)Theseregistersaremutuallyexclusivebitfields inthe32-bitPSR.Thebit assignmentsareasshown inFigure3andFigure4.Figure3.APSRIPSRandEPSRbitassignments161503130292827262524231098APSRNReservedzcvoIPSRReservedISR_NUMBEREPSRReservedICI/ITReservedICI/ITReservedMS48365V1Figure4.PSRbitassignments161510980313029282726252423N ZcvocVITTReservedICI/ITISR_NUMBERReserved-MS48366V1Access these registers individually or as a combination of any two or all three registers,usingtheregisternameasanargumenttotheMSRorMRS instructions.Forexample:Readall oftheregistersusingPSRwiththeMRSinstructionWritetotheAPSRusingAPSRwiththeMSRinstructionThePSRcombinationsandattributesare:Table3.PSRregistercombinationsTypeRegisterCombinationPSRread-write(1), (2)APSR, EPSR,and IPSRIEPSRread-onlyEPSRand IPSRread-write(1)IAPSRAPSRandIPSRread-write(2)EAPSRAPSRandEPSRTheprocessorignoreswritestotheIPSRbits12.Reads of the EPSR bits return zero, and the processor ignores writes to the these bitsSee the instruction descriptions MRS on page 100 and MSR on page 101for moreinformationabouthowtoaccesstheprogramstatusregistersA16/156DocID15491Rev6
The Cortex®-M3 processor PM0056 16/156 DocID15491 Rev 6 Program status register The Program Status Register (PSR) combines: • Application Program Status Register (APSR) • Interrupt Program Status Register (IPSR) • Execution Program Status Register (EPSR) These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments are as shown in Figure 3 and Figure 4. Figure 3. APSR, IPSR and EPSR bit assignments Figure 4. PSR bit assignments Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example: • Read all of the registers using PSR with the MRS instruction • Write to the APSR using APSR with the MSR instruction. The PSR combinations and attributes are: See the instruction descriptions MRS on page 100 and MSR on page 101 for more information about how to access the program status registers. Table 3. PSR register combinations Register Type Combination PSR read-write(1), (2) 1. The processor ignores writes to the IPSR bits. 2. Reads of the EPSR bits return zero, and the processor ignores writes to the these bits APSR, EPSR, and IPSR IEPSR read-only EPSR and IPSR IAPSR read-write(1) APSR and IPSR EAPSR read-write(2) APSR and EPSR 25 24 23 Reserved ISR_NUMBER 31 30 29 28 27 NZCV 0 APSR Reserved IPSR EPSR Reserved Reserved 26 16 15 10 9 ICI/IT ICI/IT T Reserved Q 8 MS48365V1 N 31 30 29 28 27 26 25 24 23 16 15 10 9 8 0 Z C V Q ICI/IT T Reserved ICI/IT ISR_NUMBER Reserved MS48366V1
TheCortex-M3processorPM0056ApplicationprogramstatusregisterThe APSR contains the current stateofthe condition flags from previous instructionexecutions.See theregister summaryinTable2onpage15for its attributes.Thebitassignments are:Table4.APSRbitdefinitionsBitsDescriptionBit 31N: Negative or less than flag:o: Operation result was positive, zero, greater than, or equal1:Operationresultwas negativeorless than.Bit 30z: Zero flag:O:Operation result was not zero1:Operation resultwas zeroBit 29C: Carry or borrow flag:O:Addoperation did not result in a carrybit or subtract operationresulted in aborrowbit1:Add operation resulted in a carry bit or subtract operation did not result in aborrow bit.Bit 28v: Overflow flag:O: Operation did not result in an overflow1:Operation resulted inanoverflow.Bit 27Q: Sticky saturation flag:O: Indicates thatsaturation has not occurred since resetor since thebit was lastcleared to zero1: Indicates when an SSATor USAT instruction results in saturation.This bit is cleared to zero by software using an MRS instruction.Reserved.Bits 26:0A17/156DocID15491Rev6
DocID15491 Rev 6 17/156 PM0056 The Cortex®-M3 processor 155 Application program status register The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 2 on page 15 for its attributes. The bit assignments are: Table 4. APSR bit definitions Bits Description Bit 31 N: Negative or less than flag: 0: Operation result was positive, zero, greater than, or equal 1: Operation result was negative or less than. Bit 30 Z: Zero flag: 0: Operation result was not zero 1: Operation result was zero. Bit 29 C: Carry or borrow flag: 0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit. Bit 28 V: Overflow flag: 0: Operation did not result in an overflow 1: Operation resulted in an overflow. Bit 27 Q: Sticky saturation flag: 0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero 1: Indicates when an SSAT or USAT instruction results in saturation. This bit is cleared to zero by software using an MRS instruction. Bits 26:0 Reserved
TheCortex-M3processorPM0056InterruptprogramstatusregisterTheIPSRcontainstheexceptiontypenumberof thecurrentInterruptServiceRoutine(ISR).See theregistersummary in Table2on page15for itsattributes.The bit assignmentsare:Table5.IPSRbitdefinitionsBitsDescriptionBits 31:9ReservedBits 8:0ISR_NUMBER:This is thenumberof thecurrentexception:O: Thread mode1:Reserved2: NMI3: Hard fault4:Memorymanagementfault5: Bus fault6:Usagefault7:Reserved...10:Reserved11: SVCall12:ReservedforDebug13:Reserved14:PendSV15:SysTick16:IRQ0(1).....83: IRQ67(1)seeExceptiontypesonpage32formoreinformation.1.See STM32 product reference manual/datasheet for more information on interrupt mappingA18/156DocID15491Rev6
The Cortex®-M3 processor PM0056 18/156 DocID15491 Rev 6 Interrupt program status register The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). See the register summary in Table 2 on page 15 for its attributes. The bit assignments are: Table 5. IPSR bit definitions Bits Description Bits 31:9 Reserved Bits 8:0 ISR_NUMBER: This is the number of the current exception: 0: Thread mode 1: Reserved 2: NMI 3: Hard fault 4: Memory management fault 5: Bus fault 6: Usage fault 7: Reserved . 10: Reserved 11: SVCall 12: Reserved for Debug 13: Reserved 14: PendSV 15: SysTick 16: IRQ0(1) . . 83: IRQ67(1) see Exception types on page 32 for more information. 1. See STM32 product reference manual/datasheet for more information on interrupt mapping
PM0056TheCortex-M3processorExecutionprogramstatusregisterTheEPSRcontainstheThumb statebit,andtheexecution statebitsforeithertheIf-Then(IT)instructionInterruptible-ContinuableInstruction(iCl)fieldforaninterruptedloadmultipleorstoremultipleinstructionSeetheregistersummaryinTable2onpage15fortheEPSRattributes.Thebitassignments are:Table6.EPSRbit definitionsBitsDescriptionBits 31:27ReservedBits26:25,15:10ICl:Interruptible-continuable instructionbitsSee Interruptible-continuable instructions onpage19Bits 26:25,15:10IT:Indicates the execution statebitsof theIT instruction,seeITonpage94.Bit 24Always set to 1.Bits 23:16Reserved.Bits 9:0]Reserved.AttemptstoreadtheEPSRdirectlythroughapplicationsoftwareusingtheMSRinstructionalwaysreturnzero.AttemptstowritetheEPSRusingtheMSRinstructioninapplicationsoftwareareignored.FaulthandlerscanexamineEPSRvalue inthestackedPSRtoindicatetheoperationthatisatfault.SeeSection2.3.7:Exceptionentryandreturnonpage 37Interruptible-continuableinstructionsWhen an interrupt occurs during the execution of an LDM or STM instruction, the processor:Stops the load multiple or store multiple instruction operation temporarilyStoresthenextregisteroperandinthemultipleoperationtoEPSRbits[15:12]Afterservicingtheinterrupt,theprocessor:Returnstotheregisterpointedtobybits[15:12]Resumesexecutionofthemultipleloadorstore instruction.When theEPSRholdsIClexecutionstate, bits[26:25,11:10] arezero.If-ThenblockTheIf-Thenblockcontainsuptofourinstructionsfollowinga16-bitITinstruction.Eachinstruction intheblock isconditional.Theconditionsforthe instructions areeitherallthesame,orsomecanbethe inverseof others.SeeITonpage94formore information.ExceptionmaskregistersTheexceptionmaskregistersdisablethehandlingofexceptionsbytheprocessor.Disableexceptionswheretheymight impactontimingcritical tasks.SDocID15491Rev619/156
DocID15491 Rev 6 19/156 PM0056 The Cortex®-M3 processor 155 Execution program status register The EPSR contains the Thumb state bit, and the execution state bits for either the: • If-Then (IT) instruction • Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. See the register summary in Table 2 on page 15 for the EPSR attributes. The bit assignments are: Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are ignored. Fault handlers can examine EPSR value in the stacked PSR to indicate the operation that is at fault. See Section 2.3.7: Exception entry and return on page 37 Interruptible-continuable instructions When an interrupt occurs during the execution of an LDM or STM instruction, the processor: • Stops the load multiple or store multiple instruction operation temporarily • Stores the next register operand in the multiple operation to EPSR bits[15:12]. After servicing the interrupt, the processor: • Returns to the register pointed to by bits[15:12] • Resumes execution of the multiple load or store instruction. When the EPSR holds ICI execution state, bits[26:25,11:10] are zero. If-Then block The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See IT on page 94 for more information. Exception mask registers The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks. Table 6. EPSR bit definitions Bits Description Bits 31:27 Reserved. Bits 26:25, 15:10 ICI: Interruptible-continuable instruction bits See Interruptible-continuable instructions on page 19. Bits 26:25, 15:10 IT: Indicates the execution state bits of the IT instruction, see IT on page 94. Bit 24 Always set to 1. Bits 23:16 Reserved. Bits 9:0] Reserved
TheCortex-M3processorPM0056ToaccesstheexceptionmaskregistersusetheMSRandMRSinstructions,ortheCPSinstructiontochangethevalueofPRIMASKorFAULTMASK.SeeMRSonpage100,MSRon page 101, and CPs on page 98for more information.Prioritymask registerThePRIMASKregisterpreventsactivationofallexceptionswithconfigurablepriority.SeetheregistersummaryinTable2onpage15foritsattributes.Figure5showsthebitassignmentsFigure5.PRIMASKbitassignments31ReservedPRIMASK MSv39638V1Table7.PRIMASK registerbitdefinitionsBitsDescriptionBits 31:1ReservedPRIMASK:Bit oO:No effect1: Prevents the activation of all exceptions with configurable priority.FaultmaskregisterTheFAULTMASKregisterpreventsactivationofallexceptionsexceptforNon-MaskableInterrupt (NMI). See the register summary in Table 2 on page 15 for its attributes. Figure 6showsthebitassignmentsFigure6.FAULTMASKbitassignments31ReservedFAULTMASKMSv39639V1Table8.FAULTMASKregisterbitdefinitionSBitsFunctionBits 31:1ReservedBit OFAULTMASK:O:No effect1:PreventstheactivationofallexceptionsexceptforNMl.A20/156DocID15491Rev6
The Cortex®-M3 processor PM0056 20/156 DocID15491 Rev 6 To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. See MRS on page 100, MSR on page 101, and CPS on page 98 for more information. Priority mask register The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary in Table 2 on page 15 for its attributes. Figure 5 shows the bit assignments. Figure 5. PRIMASK bit assignments Fault mask register The FAULTMASK register prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). See the register summary in Table 2 on page 15 for its attributes. Figure 6 shows the bit assignments. Figure 6. FAULTMASK bit assignments Table 7. PRIMASK register bit definitions Bits Description Bits 31:1 Reserved Bit 0 PRIMASK: 0: No effect 1: Prevents the activation of all exceptions with configurable priority. Table 8. FAULTMASK register bit definitions Bits Function Bits 31:1 Reserved Bit 0 FAULTMASK: 0: No effect 1: Prevents the activation of all exceptions except for NMI. MSv39638V1 31 Reserved 1 0 PRIMASK MSv39639V1 Reserved 31 1 0 FAULTMASK