TheCortex-M3processorPM00562.2.3BehaviorofmemoryaccessesThebehaviorofaccessestoeachregioninthememorymapis:Table12.MemoryaccessbehaviorAddressMemoryMemoryXNDescriptiontyperangeregionExecutableregion forprogramcode.Nomal(1)Code0x00000000-0x1FFFFFFFYou can also put data here.Executable regionfordata.You canalso put code here.Normal(1)SRAM0x20000000-0x3FFFFFFFThis region includesbitbandandbitband alias areas, see Table 13onpage 28.This region includes bit band and bitDevice(1)XN(1)band alias areas,seeTable 14on0x40000000-0x5FFFFFFFPeripheralpage 28.ExternalNormal(1)0x60000000-0x9FFFFFFFExecutableregionfordata.RAMExternalDevice(1)XN(1)0xA0000000-0xDFFFFFFFExternal Device memorydevicePrivateThis region includes the NVIC,Strongly-XN(1)Systemtimerandsystemcontrol0xE0000000-0xE00FFFFFPeripheralordered(1)Busblock.MemoryThis region includes all the STM32Device(1)XN(1)0xE0100000-0xFFFFFFFFmappedstandard peripherals.peripherals1.See Memory regions, types and attributes on page 25 for more information.TheCode,SRAM,andexternalRAMregionscanholdprograms.However,itisrecommendedthatprogramsalwaysusetheCoderegion.This isbecausetheprocessorhasseparatebusesthatenableinstructionfetchesanddataaccessestooccursimultaneously.2.2.4SoftwareorderingofmemoryaccessesThe order of instructions in the program flow does not always guarantee the order of thecorrespondingmemorytransactions.Thisisbecause:-Theprocessorcanreordersomememoryaccessestoimproveefficiency.providingthisdoesnotaffectthebehavioroftheinstructionsequenceTheprocessorhasmultiplebusinterfacesMemoryordevices inthememorymaphavedifferentwait states.SomememoryaccessesarebufferedorspeculativeSection2.2.2:Memorysystemorderingofmemoryaccessesonpage25describesthecaseswherethememorysystemguaranteestheorderofmemoryaccesses.Otherwise,iftheorderofmemoryaccessesiscritical,softwaremust includememorybarrierinstructionstoforcethatordering.Theprocessorprovidesthefollowingmemorybarrier instructions:S26/156DocID15491Rev6
The Cortex®-M3 processor PM0056 26/156 DocID15491 Rev 6 2.2.3 Behavior of memory accesses The behavior of accesses to each region in the memory map is: The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that programs always use the Code region. This is because the processor has separate buses that enable instruction fetches and data accesses to occur simultaneously. 2.2.4 Software ordering of memory accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. This is because: • The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. • The processor has multiple bus interfaces • Memory or devices in the memory map have different wait states • Some memory accesses are buffered or speculative. Section 2.2.2: Memory system ordering of memory accesses on page 25 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The processor provides the following memory barrier instructions: Table 12. Memory access behavior Address range Memory region Memory type XN Description 0x00000000- 0x1FFFFFFF Code Normal (1) 1. See Memory regions, types and attributes on page 25 for more information. - Executable region for program code. You can also put data here. 0x20000000- 0x3FFFFFFF SRAM Normal (1) - Executable region for data. You can also put code here. This region includes bit band and bit band alias areas, see Table 13 on page 28. 0x40000000- 0x5FFFFFFF Peripheral Device (1) XN (1) This region includes bit band and bit band alias areas, see Table 14 on page 28. 0x60000000- 0x9FFFFFFF External RAM Normal (1) - Executable region for data. 0xA0000000- 0xDFFFFFFF External device Device (1) XN (1) External Device memory 0xE0000000- 0xE00FFFFF Private Peripheral Bus Stronglyordered (1) XN (1) This region includes the NVIC, System timer, and system control block. 0xE0100000- 0xFFFFFFFF Memory mapped peripherals Device (1) XN (1) This region includes all the STM32 standard peripherals
TheCortex-M3processorPM0056DMBThe Data Memory Barrier (DMB) instruction ensures that outstandingmemorytransactionscompletebeforesubsequentmemorytransactions.See DMB on page 99.DSBTheDataSynchronizationBarrier(DSB)instructionensuresthatoutstandingmemorytransactionscompletebeforesubsequentinstructions execute.SeeDSB onpage 100ISBTheInstructionSynchronizationBarrier(ISB)ensuresthattheeffectofallcompletedmemorytransactionsisrecognizablebysubsequentinstructions.SeeISBonpage100Usememorybarrierinstructions in,forexample:Vectortable.If theprogramchangesanentryinthevectortable,andthenenablesthecorresponding exception,usea DMBinstructionbetweentheoperations.This ensuresthatiftheexceptionistaken immediatelyafterbeingenabledtheprocessorusesthenewexceptionvector.Self-modifying code.If aprogram contains self-modifying code,use an ISBinstruction immediatelyafterthecodemodification in theprogram.This ensuressubsequentinstruction executionuses theupdated program.Memorymapswitching.IfthesystemcontainsamemorymapswitchingmechanismuseaDSBinstructionafterswitchingthememorymapintheprogram.This ensuressubsequent instructionexecutionusestheupdatedmemorymap.Dynamicexceptionprioritychange.Whenanexceptionpriorityhastochangewhentheexception ispendingoractive,useDSBinstructionsafterthechange.This ensuresthechangetakeseffectoncompletionoftheDSB instruction.Usingasemaphoreinmulti-mastersystem.Ifthesystemcontainsmorethanonebusmaster,forexampleifanotherprocessorispresentinthesystem,eachprocessormustuseaDMBinstructionafteranysemaphore instructions,toensureotherbusmastersseethememorytransactionsintheorderinwhichtheywereexecutedMemoryaccessestoStrongly-orderedmemory,suchasthesystemcontrolblock,donotrequiretheuseofDMBinstructions2.2.5Bit-bandingAbit-band regionmaps eachword inabit-bandalias regionto a singlebit in thebit-bandregion.Thebit-bandregionsoccupythelowest1MBoftheSRAMandperipheralmemoryregionsThememorymaphastwo32MBaliasregionsthatmaptotwo1MBbit-bandregions:Accessestothe32MBSRAMaliasregionmaptothe1MBSRAMbit-bandregion,asshowninTable13Accessestothe32MBperipheralaliasregionmaptothe1MBperipheralbit-bandregion,asshowninTable14.A27/156DocID15491Rev6
DocID15491 Rev 6 27/156 PM0056 The Cortex®-M3 processor 155 Use memory barrier instructions in, for example: • Vector table. If the program changes an entry in the vector table, and then enables the corresponding exception, use a DMB instruction between the operations. This ensures that if the exception is taken immediately after being enabled the processor uses the new exception vector. • Self-modifying code. If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. This ensures subsequent instruction execution uses the updated program. • Memory map switching. If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. This ensures subsequent instruction execution uses the updated memory map. • Dynamic exception priority change. When an exception priority has to change when the exception is pending or active, use DSB instructions after the change. This ensures the change takes effect on completion of the DSB instruction. • Using a semaphore in multi-master system. If the system contains more than one bus master, for example, if another processor is present in the system, each processor must use a DMB instruction after any semaphore instructions, to ensure other bus masters see the memory transactions in the order in which they were executed. Memory accesses to Strongly-ordered memory, such as the system control block, do not require the use of DMB instructions. 2.2.5 Bit-banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions: • Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as shown in Table 13 • Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band region, as shown in Table 14. DMB The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. See DMB on page 99. DSB The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. See DSB on page 100. ISB The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. See ISB on page 100
TheCortex-M3processorPM0056Table13.SRAMmemorybit-bandingregionsAddressMemoryInstruction and dataaccessesregionrange0x20000000-Directaccessestothismemoryrangebehaveas SRAM memorySRAM bit-band regionOx200FFFFFaccesses,butthisregionisalsobitaddressablethroughbit-bandaliasData accesses to this region are remapped to bitbandregion.Awrite0x22000000-SRAMbit-bandaliasoperation isperformedasread-modify-write.Instructionaccessesarenot0x23FFFFFFremappedTable 14.Peripheral memory bit-banding regionsAddressMemoryInstructionanddataaccessesrangeregionDirect accesses to this memoryrange behave as peripheral memory0x40000000-Peripheralaccesses,butthisregionisalsobitaddressablethroughbit-bandbit-bandregion0x400FFFFFalias.Dataaccessestothisregionareremappedtobit-bandregion.Awrite0x42000000-Peripheraloperationisperformedasread-modify-write.Instructionaccessesarebit-band alias0x43FFFFFFnotpermittedA wordaccess to the SRAMorperipheral bit-band alias regionsmaptoa singlebit in theSRAMorperipheralbit-band region.Thefollowingformulashowshowthealias regionmapsontothebit-bandregion:bit_word_offset = (byte_offset x 32) + (bit_number x 4)bit_word_addr = bit_band_base +bit_word_offsetWhere:Bit_word_offset is the position of the target bit in the bit-band memory region.Bit_word_addris the address of the word in the alias memory region that maps to thetargeted bit.Bit_band_baseis the startingaddressofthealias region.Byte_offset is thenumberof the byte in the bit-bandregion that contains thetargetedbit.Bit_numberis thebit position, O-7,of the targeted bit.Figure10on page29 shows examples of bit-bandmappingbetween the SRAMbit-bandaliasregionandtheSRAMbit-band region:ThealiaswordatOx23FFFFEOmapstobit[O]of thebit-bandbyteat0x200FFFFF:0x23FFFFE0=0x22000000+(0xFFFFF*32)+(0*4)Thealiaswordat Ox23FFFFFCmapstobit[7] of thebit-bandbyteat0x200FFFFF: 0x23FFFFFC =0x22000000+(0xFFFFF*32)+(7*4).Thealias word at 0x22000000 maps tobit[0] ofthe bit-band byteat0x20000000:0x22000000=0x22000000+(0*32)+(0*4).The alias word at 0x2200001C maps to bit[7] of the bit-band byte at0x20000000:0x2200001C=0x22000000+(0*32)+(7*4)。A28/156DocID15491Rev6
The Cortex®-M3 processor PM0056 28/156 DocID15491 Rev 6 A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bit-band region. The following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset Where: • Bit_word_offset is the position of the target bit in the bit-band memory region. • Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. • Bit_band_base is the starting address of the alias region. • Byte_offset is the number of the byte in the bit-band region that contains the targeted bit. • Bit_number is the bit position, 0-7, of the targeted bit. Figure 10 on page 29 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region: • The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x200FFFFF: 0x23FFFFE0 = 0x22000000 + (0xFFFFF*32) + (0*4). • The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF: 0x23FFFFFC = 0x22000000 + (0xFFFFF*32) + (7*4). • The alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000: 0x22000000 = 0x22000000 + (0*32) + (0 *4). • The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x20000000: 0x2200001C = 0x22000000+ (0*32) + (7*4). Table 13. SRAM memory bit-banding regions Address range Memory region Instruction and data accesses 0x20000000- 0x200FFFFF SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. 0x22000000- 0x23FFFFFF SRAM bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. Table 14. Peripheral memory bit-banding regions Address range Memory region Instruction and data accesses 0x40000000- 0x400FFFFF Peripheral bit-band region Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. 0x42000000- 0x43FFFFFF Peripheral bit-band alias Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted
PM0056TheCortex-M3processorFigure 10.Bit-band mapping32MB alias region0x23FFFFFC0x23FFFFF80x23FFFFF40x23FFFFF00x23FFFFEC0x23FFFFE80x23FFFFE40x23FFFFE0。0x2200001C0x220000000x220000180x220000140x220000100x22000000x220000080x220000041MB SRAM bit-band regior0x200FFFFF0x200FFFFE0x200FFFFx200FFFFC0x20000030x20000000x200000020x20000001MS48369V1Directlyaccessing analias regionWriting to a word in the alias region updates a single bit in the bit-band region.Bit[0] of the value written to a word in the alias regiondetermines the value written to thetargeted bit in the bit-band region. Writing a value with bit[o] set to 1 writes a 1to the bit-bandbit,andwritingavaluewithbitjolsettoOwritesaOtothebit-bandbitBits[31:1] ofthe alias word haveno effecton thebit-bandbit.Writing Ox01has the sameeffectaswritingOxFF.WritingOxoohasthesameeffectaswritingOx0EReadingawordinthealiasregion:Ox0000000oindicatesthatthetargetedbit inthebit-bandregion issettozero0x00000001 indicates that the targeted bit in the bit-band region is set to 1Directlyaccessingabit-bandregionBehaviorofmemory accesses on page 26describes thebehavior of direct byte, halfword,orwordaccessestothebit-bandregions.2.2.6MemoryendiannessTheprocessorviewsmemoryasalinearcollectionofbytesnumberedinascendingorderfromzero.Forexample,bytes0-3holdthefirststoredword,andbytes4-7holdthesecondstored word.Little-endianformatIn little-endianformat,theprocessorstorestheleastsignificant byteofawordatthelowest-numbered byte,and themost significant byteatthehighest-numbered byte.SeeFigure11foranexampleDocID15491Rev629/156
DocID15491 Rev 6 29/156 PM0056 The Cortex®-M3 processor 155 Figure 10. Bit-band mapping Directly accessing an alias region Writing to a word in the alias region updates a single bit in the bit-band region. Bit[0] of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit[0] set to 1 writes a 1 to the bitband bit, and writing a value with bit[0] set to 0 writes a 0 to the bit-band bit. Bits[31:1] of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. Reading a word in the alias region: • 0x00000000 indicates that the targeted bit in the bit-band region is set to zero • 0x00000001 indicates that the targeted bit in the bit-band region is set to 1 Directly accessing a bit-band region Behavior of memory accesses on page 26 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 2.2.6 Memory endianness The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Little-endian format In little-endian format, the processor stores the least significant byte of a word at the lowestnumbered byte, and the most significant byte at the highest-numbered byte. See Figure 11 for an example. 0x23FFFFE4 0x22000004 0x23FFFFFC 0x23FFFFF8 0x23FFFFF4 0x23FFFFF0 0x23FFFFEC 0x23FFFFE8 0x23FFFFE0 0x2200001C 0x22000018 0x22000014 0x22000010 0x2200000C 0x22000008 0x22000000 32MB alias region 0 7 0 7 0 0x20000003 0x20000002 0x20000001 0x20000000 6 5 4 3 2 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0x200FFFFF 0x200FFFFE 0x200FFFFD 0x200FFFFC 1MB SRAM bit-band region MS48369V1
TheCortex-M3processorPM0056Figure11.Little-endianexampleMemoryRegister7031242316158.7UBOB3B2B1BOAddressAIsbyteB1A+1B2A+2A+3B3msbyteMSv39644V12.2.7Synchronization primitivesTheCortex-M3 instructionsetincludespairsofsynchronizationprimitives.Theseprovideanon-blocking mechanismthat athread or process canusetoobtain exclusive access toamemorylocation.Softwarecanusethemtoperformaguaranteedread-modify-writememoryupdatesequence,orforasemaphoremechanism.Apairofsynchronizationprimitivescomprises:ALoad-ExclusiveinstructionUsed to read thevalue ofa memory location, requestingexclusiveaccesstothatlocationAStore-ExclusiveinstructionUsedtoattempttowritetothesamememorylocation,returning a status bit to a register.If this bit is:O:it indicates thatthethread orprocessgainedexclusiveaccesstothememory,andthewritesucceeds1:it indicatesthatthethread orprocessdid notgainexclusive access to the memory, and no write isperformedThepairsof Load-ExclusiveandStore-Exclusive instructionsareThewordinstructionsLDREXandSTREXThehalfwordinstructionsLDREXHandSTREXHThebyteinstructionsLDREXBandSTREXBSoftwaremustusea Load-ExclusiveinstructionwiththecorrespondingStore-Exclusiveinstruction.To perform a guaranteed read-modify-write of a memory location, software must:1.Use a Load-Exclusive instructionto read the value of the location.2.Updatethevalue,asrequired3.UseaStore-Exclusive instructiontoattempttowritethenewvaluebacktothememorylocation,andteststhereturned status bit.Ifthis bit is:O:Theread-modify-writecompleted successfully,1:Nowritewasperformed.This indicates thatthevaluereturnedatstep1mightbeout ofdate.The software must retry the read-modify-write sequence,A30/156DocID15491Rev6
The Cortex®-M3 processor PM0056 30/156 DocID15491 Rev 6 Figure 11. Little-endian example 2.2.7 Synchronization primitives The Cortex-M3 instruction set includes pairs of synchronization primitives. These provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism. A pair of synchronization primitives comprises: The pairs of Load-Exclusive and Store-Exclusive instructions are: • The word instructions LDREX and STREX • The halfword instructions LDREXH and STREXH • The byte instructions LDREXB and STREXB. Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform a guaranteed read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Update the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location, and tests the returned status bit. If this bit is: 0: The read-modify-write completed successfully, 1: No write was performed. This indicates that the value returned at step 1 might be out of date. The software must retry the read-modify-write sequence, MSv39644V1 Memory Register Address A A+1 lsbyte msbyte A+2 A+3 7 0 B3 B2 B1 B0 31 2423 1615 8 7 0 B0 B1 B2 B3 A Load-Exclusive instruction Used to read the value of a memory location, requesting exclusive access to that location. A Store-Exclusive instruction Used to attempt to write to the same memory location, returning a status bit to a register. If this bit is: 0: it indicates that the thread or process gained exclusive access to the memory, and the write succeeds 1: it indicates that the thread or process did not gain exclusive access to the memory, and no write is performed