PM0056AboutthisdocumentFigure1.STM32Cortex-M3implementationSTM32Cortex-M3processorEmbeddedProcessorNVICTrace MacrocellcoreDebugSerialTaccesswire4.portviewerFlashDatapatchwatchpointsBus matrixCodeSRAMandinterfaceperipheral interface至1++ai15994cTofacilitatethedesign of cost-sensitivedevices,theCortex-M3processor implementstightly-coupledsystemcomponentsthatreduceprocessorareawhilesignificantly improvinginterrupt handling and systemdebug capabilities.TheCortex-M3processor implements aversion oftheThumbinstruction set, ensuring high codedensity andreduced programmemoryrequirements.TheCortex-M3instructionsetprovidestheexceptionalperformanceexpectedof a modern32-bitarchitecture,with thehighcodedensityof 8-bit and16-bitmicrocontrollers.TheCortex-M3processorcloselyintegratesaconfigurablenestedinterruptcontroller(NVIC),todeliver industry-leading interrupt performance.The NVIC includes anon-maskableinterrupt(NMi),andprovidesupto256interruptprioritylevels.Thetightintegrationof theprocessorcoreandNViCprovidesfastexecutionof interruptserviceroutines(ISRs),dramaticallyreducingthe interrupt latency.This is achieved throughthehardware stacking of registers,and the ability to suspend load-multipleand store-multipleoperations.Interrupthandlersdonotrequireanyassemblerstubs,removinganycodeoverhead from the ISRs.Tail-chaining optimization also significantly reduces theoverheadwhenswitchingfromoneiSRtoanotherTooptimizelow-powerdesigns,theNViCintegrateswiththesleepmodes,thatincludeadeepsleepfunctionthatenablestheSTM32toenterSTOPorSTDBYmode1.3.1SystemlevelinterfaceThe Cortex-M3 processor provides multiple interfaces using AMBAtechnology to providehighspeed,lowlatencymemoryaccesses.Itsupportsunaligneddataaccessesandimplementsatomicbitmanipulationthatenablesfasterperipheralcontrols,systemspinlocks and thread-safe Boolean data handling.S11/156DocID15491Rev6
DocID15491 Rev 6 11/156 PM0056 About this document 155 Figure 1. STM32 Cortex-M3 implementation To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction set, ensuring high code density and reduced program memory requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M3 processor closely integrates a configurable nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require any assembler stubs, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the STM32 to enter STOP or STDBY mode. 1.3.1 System level interface The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide high speed, low latency memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data handling. Debug access port NVIC ai15994c Processor core STM32 Cortex-M3 processor Embedded Trace Macrocell Flash patch Data watchpoints Serial wire viewer SRAM and peripheral interface Bus matrix Code interface
PM0056Aboutthisdocument1.3.2IntegratedconfigurabledebugTheCortex-M3processorimplementsacompletehardwaredebugsolution.Thisprovideshighsystemvisibilityoftheprocessorandmemorythrougheitheratraditional JTAGportora2-pinSerialWireDebug(SWD)portthat isidealforsmallpackagedevicesForsystemtracetheprocessorintegratesanInstrumentationTraceMacrocell (ITM)alongsidedatawatchpointsandaprofilingunit.Toenablesimpleandcost-effectiveprofilingof the systemeventsthesegenerate,a Serial WireViewer(Sw)canexportastreamofsoftware-generatedmessages,datatrace,andprofilinginformationthroughasinglepin.TheoptionalEmbeddedTraceMacrocell"(ETM)delivers unrivalled instructiontracecaptureinanareafarsmallerthantraditionaltraceunits,enablingmanylowcostMCUstoimplementfull instructiontracefor thefirst time.Cortex-M3 processor features and benefits summary1.3.3Tight integrationofsystemperipheralsreducesareaanddevelopmentcostsThumbinstructionsetcombineshighcodedensitywith32-bitperformanceCode-patchabilityforROMsystemupdatesPowercontroloptimizationofsystemcomponentsIntegratedsleepmodesforlowpowerconsumptionFastcodeexecutionpermitsslowerprocessorclockorincreasessleepmodetimeHardware division and fast multiplierDeterministic,high-performance interrupt handling fortime-critical applicationsExtensivedebugandtracecapabilities:Serial WireDebugandSerial WireTracereducethenumberofpinsrequiredfordebugging and tracing1.3.4Cortex-M3coreperipheralsThese are:Nested vectored interrupt controllerThenestedvectored interruptcontroller(NViC)isanembedded interruptcontrollerthatsupports lowlatency interruptprocessingSystemcontrol blockThesystemcontrolblock(SCB)istheprogrammersmodelinterfacetotheprocessor.Itprovides system implementation information and system control, includingconfiguration,control,andreporting ofsystemexceptions.SystemtimerThesystemtimer,SysTick,isa24-bitcount-downtimer.UsethisasaReal TimeOperatingSystem(RTOS)ticktimerorasasimplecounter.A12/156DocID15491Rev6
About this document PM0056 12/156 DocID15491 Rev 6 1.3.2 Integrated configurable debug The Cortex-M3 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for small package devices. For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. The optional Embedded Trace Macrocell™ (ETM) delivers unrivalled instruction trace capture in an area far smaller than traditional trace units, enabling many low cost MCUs to implement full instruction trace for the first time. 1.3.3 Cortex®-M3 processor features and benefits summary • Tight integration of system peripherals reduces area and development costs • Thumb instruction set combines high code density with 32-bit performance • Code-patch ability for ROM system updates • Power control optimization of system components • Integrated sleep modes for low power consumption • Fast code execution permits slower processor clock or increases sleep mode time • Hardware division and fast multiplier • Deterministic, high-performance interrupt handling for time-critical applications • Extensive debug and trace capabilities: – Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing. 1.3.4 Cortex®-M3 core peripherals These are: Nested vectored interrupt controller The nested vectored interrupt controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing. System control block The system control block (SCB) is the programmers model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions. System timer The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System (RTOS) tick timer or as a simple counter
PM0056TheCortex-M3processor2The Cortex-M3 processor2.1ProgrammersmodelThis section describes the Cortex-M3programmers model. In addition to the individual coreregisterdescriptions,itcontainsinformationabouttheprocessormodesandprivilegelevelsforsoftwareexecutionand stacks.2.1.1Processormodeand privilege levelsforsoftwareexecutionTheprocessormodesare:Thread modeUsedtoexecuteapplicationsoftware.TheprocessorentersThreadmodewhen it comes out of reset.HandlermodeUsedtohandleexceptions.TheprocessorreturnstoThreadmodewhen ithasfinishedexceptionprocessingTheprivilegelevelsforsoftwareexecutionareUnprivilegedThe software:HaslimitedaccesstotheMSRandMRSinstructions,andcannotusetheCPSinstructionCannotaccessthesystemtimer,NViC,orsystemcontrolblockMight have restricted access to memory or peripherals.Unprivileged software executes at the unprivileged level.PrivilegedThe softwarecanuseall theinstructions andhasaccesstoallresources.Privilegedsoftware executes at theprivileged level.InThreadmode,theCONTROLregistercontrolswhethersoftwareexecutionisprivilegedorunprivileged, see CONTROL register on page 21. In Handler mode, software execution isalwaysprivilegedOnly privileged software can write to the CONTROLregister to change the privilege level forsoftwareexecutioninThreadmode.UnprivilegedsoftwarecanusetheSvCinstructiontomakeasupervisorcalltotransfercontroltoprivilegedsoftware2.1.2StacksTheprocessorusesafulldescendingstack.Thismeansthestackpointerindicatesthelaststackeditemonthestackmemory.Whentheprocessorpushesanewitemontothestack,itdecrementsthestackpointerandthenwritesthe itemtothenewmemorylocation.Theprocessorimplementstwostacks,themainstackandtheprocessstack,withindependentcopiesofthestackpointer,seeStackpointeronpage15S13/156DocID15491Rev6
DocID15491 Rev 6 13/156 PM0056 The Cortex®-M3 processor 155 2 The Cortex®-M3 processor 2.1 Programmers model This section describes the Cortex-M3 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 2.1.1 Processor mode and privilege levels for software execution The processor modes are: The privilege levels for software execution are: In Thread mode, the CONTROL register controls whether software execution is privileged or unprivileged, see CONTROL register on page 21. In Handler mode, software execution is always privileged. Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. 2.1.2 Stacks The processor uses a full descending stack. This means the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements two stacks, the main stack and the process stack, with independent copies of the stack pointer, see Stack pointer on page 15. Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. Handler mode Used to handle exceptions. The processor returns to Thread mode when it has finished exception processing. Unprivileged The software: • Has limited access to the MSR and MRS instructions, and cannot use the CPS instruction • Cannot access the system timer, NVIC, or system control block • Might have restricted access to memory or peripherals. Unprivileged software executes at the unprivileged level. Privileged The software can use all the instructions and has access to all resources. Privileged software executes at the privileged level
TheCortex-M3processorPM0056InThreadmode,theCONTROLregistercontrolswhethertheprocessorusesthemainstackortheprocessstack,seeCONTROLregisteronpage21.InHandlermode,theprocessoralwaysuses themain stack.Theoptionsforprocessoroperations are:Table1.Summaryofprocessormode,executionprivilegelevel,andstackuseoptionsProcessorUsedtoPrivilege level forStackusedmodeexecutesoftwareexecutionThreadPrivileged or unprivileged (1)Main stack or process stack(1)ApplicationsHandlerExceptionhandlersAlways privilegedMainstack1.SeeCONTROLregisteronpage21.2.1.3Core registersFigure2.ProcessorcoreregistersROR1R2R3LowregistersR4R5R6General-purposeregistersR7R8R9R10HighregistersR11R12PSP*MSB**BankedversionStack pointerSP (R13)of SPLink registerLR (R14)Program counterPC (R15)PSRProgram status registerPRIMASKFAULTMASKExceptionmaskregistersSpecial registersBASEPRICONTROLregisterCONTROLMSv48364V1A14/156DocID15491Rev6
The Cortex®-M3 processor PM0056 14/156 DocID15491 Rev 6 In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack, see CONTROL register on page 21. In Handler mode, the processor always uses the main stack. The options for processor operations are: 2.1.3 Core registers Figure 2. Processor core registers Table 1. Summary of processor mode, execution privilege level, and stack use options Processor mode Used to execute Privilege level for software execution Stack used Thread Applications Privileged or unprivileged (1) 1. See CONTROL register on page 21. Main stack or process stack (1) Handler Exception handlers Always privileged Main stack Low registers High registers Stack pointer Link register Program counter MSv48364V1 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PSP* MSB* *Banked version of SP Special registers Program status register Exception mask registers CONTROL CONTROL register BASEPRI FAULTMASK PRIMASK PSR PC (R15) LR (R14) SP (R13) General-purpose registers
The Cortex-M3processorPM0056Table2.CoreregistersetsummaryRequiredResetType(1)NameDescriptionprivilege(2)valueRO-R12read-writeEitherUnknownGeneral-purpose registers on page 15MSPread-writePrivilegedStack pointeronpage15See descriptionPSPEitherread-writeUnknownStack pointer on page 15LREitherOXFFFFFFFFread-writeLink registeron page15PCread-writeEitherSee descriptionProgramcounteronpage15PSRread-writePrivileged0x01000000Programstatus registeronpage16Application program status register onASPREitherread-write0x00000000page17InterruptprogramstatusregisteronIPSRread-onlyPrivileged0x00000000page18Execution program status registeronEPSRread-onlyPrivileged0x01000000page19PRIMASKPrivilegedread-write0x00000000Priority mask register on page 20FAULTMASKread-writePrivileged0x00000000Fault mask registeronpage20BASEPRIPrivileged0x00000000read-writeBaseprioritymaskregisteronpage21CONTROLread-writePrivileged0x00000000CONTROL register on page 211.Describesaccess type during programexecution in threadmodeand Handlermode.Debugaccess candiffer.2.An entry of Either means privileged and unprivileged software can access the register.General-purpose registersRo-R12 are 32-bit general-purpose registers for data operations.Stack pointerTheStackPointer(SP)isregisterR13.InThreadmode,bit[1]oftheCONTROLregisterindicates the stack pointer to use:O=Main Stack Pointer(MSP).This is the resetvalue..1=ProcessStackPointer(PSP)Onreset,theprocessorloadstheMSPwiththevaluefromaddressOx00000000.Link registerTheLink Register(LR)isregisterR14.It stores thereturn informationforsubroutinesfunctioncalls,andexceptions.Onreset,theprocessorloadstheLRvalueOxFFFFFFFFProgram counterThe Program Counter(PC) is register R15. It contains the current program address. Bit[0j isalwaysobecauseinstructionfetchesmustbehalfwordaligned.Onreset,theprocessorloadsthePCwiththevalueoftheresetvector,whichisataddress0x00000004.15/156DoclD15491Rev6
DocID15491 Rev 6 15/156 PM0056 The Cortex®-M3 processor 155 General-purpose registers R0-R12 are 32-bit general-purpose registers for data operations. Stack pointer The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use: • 0 = Main Stack Pointer (MSP). This is the reset value. • 1 = Process Stack Pointer (PSP). On reset, the processor loads the MSP with the value from address 0x00000000. Link register The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the processor loads the LR value 0xFFFFFFFF. Program counter The Program Counter (PC) is register R15. It contains the current program address. Bit[0] is always 0 because instruction fetches must be halfword aligned. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x00000004. Table 2. Core register set summary Name Type (1) 1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ. Required privilege (2) 2. An entry of Either means privileged and unprivileged software can access the register. Reset value Description R0-R12 read-write Either Unknown General-purpose registers on page 15 MSP read-write Privileged See description Stack pointer on page 15 PSP read-write Either Unknown Stack pointer on page 15 LR read-write Either 0xFFFFFFFF Link register on page 15 PC read-write Either See description Program counter on page 15 PSR read-write Privileged 0x01000000 Program status register on page 16 ASPR read-write Either 0x00000000 Application program status register on page 17 IPSR read-only Privileged 0x00000000 Interrupt program status register on page 18 EPSR read-only Privileged 0x01000000 Execution program status register on page 19 PRIMASK read-write Privileged 0x00000000 Priority mask register on page 20 FAULTMASK read-write Privileged 0x00000000 Fault mask register on page 20 BASEPRI read-write Privileged 0x00000000 Base priority mask register on page 21 CONTROL read-write Privileged 0x00000000 CONTROL register on page 21