ContentsPM00564.4.14..148Systemcontrolblockdesignhintsandtips4.4.15SCBregistermap1484.5.150SysTick timer (STK)4.5.1.151SysTickcontrolandstatusregister(STK_CTRL)4.5.2...152SysTickreloadvalueregister(STK_LOAD)4.5.3SysTick current value register (STK_VAL)..1534.5.4SysTick calibration value register (STK_CALIB).1534.5.5154SysTickdesignhints andtips.4.5.6154SysTickregistermap5155RevisionhistoryA6/156DocID15491Rev6
Contents PM0056 6/156 DocID15491 Rev 6 4.4.14 System control block design hints and tips . . . . . . . . . . . . . . . . . . . . . 148 4.4.15 SCB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.5 SysTick timer (STK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.5.1 SysTick control and status register (STK_CTRL) . . . . . . . . . . . . . . . . 151 4.5.2 SysTick reload value register (STK_LOAD) . . . . . . . . . . . . . . . . . . . . . 152 4.5.3 SysTick current value register (STK_VAL) . . . . . . . . . . . . . . . . . . . . . . 153 4.5.4 SysTick calibration value register (STK_CALIB) . . . . . . . . . . . . . . . . . 153 4.5.5 SysTick design hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.5.6 SysTick register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
PM0056ListoftablesList of tablesTable 1..14Summaryofprocessormode,executionprivilegelevel,andstackuseoptions..15Table 2.Coreregistersetsummary.16Table 3.PSRregistercombinations..17Table 4.APSRbit definitionsTable 5..18IPSRbitdefinitions...19Table 6.EPSRbitdefinitions.20Table 7.PRIMASKregisterbitdefinitions.20Table 8.FAULTMASKregisterbitdefinitions...21Table 9.BASEPRIregisterbitassignments...Table 10.22CONTROLregisterbitdefinitions25Table 11.Ordering ofmemoryaccesses.26Table12.Memoryaccessbehavior.28Table 13.SRAMmemorybit-banding regions.28Table 14.Peripheral memorybit-banding regions31Table 15.Ccompilerintrinsicfunctionsforexclusiveaccessinstructions..33Table 16.Propertiesofthedifferentexceptiontypes.39Table 17.Exceptionreturnbehavior..Table 18.Faults.40++.41Table 19.FaultstatusandfaultaddressregistersTable 20.44Cortex-M3 instructions....49Table 21.CMSiSintrinsicfunctionstogeneratesomeCortex-M3instructionsTable 22.50CMSiS intrinsicfunctionstoaccess the specialregisters...57Table 23.Conditioncodesuffixes....Table 24..59MemoryaccessinstructionsTable 25.62Immediate,pre-indexedandpost-indexedoffsetrangesTable 26..66label-PCoffsetranges...72Table 27.Dataprocessinginstructions..Table 28.Multiply and divide instructions...83.88Table 29.PackingandunpackinginstructionsTable 30...91Branchandcontrol instructions..Table 31..92BranchrangesTable 32...97Miscellaneous instructions.105Table 33.STM32coreperipheralregisterregionsTable 34..106Memoryattributessummary...107Table 35.TEX, C, B, and S encoding....107Table 36.Cache policyformemory attribute encoding108Table 37.AP encoding....Table 38.111MemoryregionattributesforSTM32117Table 39.ExampleSiZEfieldvalues..Table 40..117MPUregistermapandresetvalues.119Table 41.Mapping of interrupts to the interrupt variablesTable 42.IPRbitassignments..125.127Table 43.CMSISfunctionsforNVICcontrolTable 44.128NVICregistermapandresetvalues..135Table 45.Priority grouping .Table 46.138SystemfaulthandlerpriorityfieldsTable 47..148SCBregistermapandresetvalueforSTM32F2andSTM32LTable 48.SCB register map and reset values..149A7/156DocID15491Rev6
DocID15491 Rev 6 7/156 PM0056 List of tables 8 List of tables Table 1. Summary of processor mode, execution privilege level, and stack use options. . . . . . . . . 14 Table 2. Core register set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3. PSR register combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. APSR bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. IPSR bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. EPSR bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. PRIMASK register bit definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. FAULTMASK register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 9. BASEPRI register bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10. CONTROL register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11. Ordering of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12. Memory access behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 13. SRAM memory bit-banding regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 14. Peripheral memory bit-banding regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 15. C compiler intrinsic functions for exclusive access instructions . . . . . . . . . . . . . . . . . . . . . 31 Table 16. Properties of the different exception types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 17. Exception return behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 18. Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 19. Fault status and fault address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 20. Cortex-M3 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 21. CMSIS intrinsic functions to generate some Cortex-M3 instructions . . . . . . . . . . . . . . . . . 49 Table 22. CMSIS intrinsic functions to access the special registers. . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 23. Condition code suffixes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 24. Memory access instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 25. Immediate, pre-indexed and post-indexed offset ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 26. label-PC offset ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 27. Data processing instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 28. Multiply and divide instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 29. Packing and unpacking instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 30. Branch and control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 31. Branch ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 32. Miscellaneous instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 33. STM32 core peripheral register regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 34. Memory attributes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 35. TEX, C, B, and S encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 36. Cache policy for memory attribute encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 37. AP encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 38. Memory region attributes for STM32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 39. Example SIZE field values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 40. MPU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 41. Mapping of interrupts to the interrupt variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 42. IPR bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 43. CMSIS functions for NVIC control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 44. NVIC register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 45. Priority grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 46. System fault handler priority fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 47. SCB register map and reset value for STM32F2 and STM32L . . . . . . . . . . . . . . . . . . . . 148 Table 48. SCB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
ListoftablesPM0056Table 49.....154SysTickregistermap and resetvalues.....................155Table 50.Documentrevisionhistory..S8/156DocID15491Rev6
List of tables PM0056 8/156 DocID15491 Rev 6 Table 49. SysTick register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 50. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
PM0056List offiguresList of figuresFigure 1..11STM32Cortex-M3implementation..14Figure 2.Processorcoreregisters.....16Figure3.APSR, IPSR and EPSR bit assignments.16Figure 4.PSRbitassignments.............20Figure 5.PRIMASKbitassignmentsFigure 6.....20FAULTMASKbitassignments.21Figure 7.BASEPRIbitassignments21Figure 8.CONTROLbitassignments..24Figure 9.Memorymap....29Figure 10.Bit-bandmapping.30Figure 11.Little-endian example.35Figure 12.VectortableFigure 13.ASR#3.53LSR#3..53Figure 14.Figure 15.LSL#3.54Figure 16.ROR#3....5455Figure17.RRX #3110Figure 18.Subregionexample..Figure 19.NVIC_iPRxregistermapping125Figure 20.142CFSRsubregistersA9/156DocID15491Rev6
DocID15491 Rev 6 9/156 PM0056 List of figures 9 List of figures Figure 1. STM32 Cortex-M3 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2. Processor core registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3. APSR, IPSR and EPSR bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. PSR bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5. PRIMASK bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 6. FAULTMASK bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. BASEPRI bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. CONTROL bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10. Bit-band mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 11. Little-endian example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 12. Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 13. ASR#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 14. LSR#3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 15. LSL#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 16. ROR #3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 17. RRX #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 18. Subregion example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 19. NVIC_IPRx register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Figure 20. CFSR subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
AboutthisdocumentPM00561AboutthisdocumentThisdocumentprovidestheinformationrequiredforapplicationandsystem-level softwaredevelopment.Itdoesnotprovideinformationondebugcomponents,features,oroperation.This material is formicrocontroller softwareand hardware engineers,including thosewhohavenoexperienceofArmproducts.arm1.1TypographicalconventionsThetypographicalconventionsusedinthisdocumentare:italicHighlightsimportantnotes,introduces specialterminology.denotesinternalcross-references,andcitations<and >Enclosereplaceabletermsforassemblersyntaxwheretheyappearincodeorcodefragments.Forexample:LDRSB<cond><Rt>,[<Rn>,#<offset>]1.2ListofabbreviationsforregistersThe following abbreviations are used in register descriptions:read/write (rw)Software can read and write to these bits.read-only (r)Softwarecanonlyreadthesebitswrite-only (w)Software can only write to this bit. Reading the bit returns the resetvalue.read/clear(rc_w1)Softwarecanreadaswell asclearthisbitbywriting1.Writing'O'hasno effect on thebit value.read/clear (rc_wo)Softwarecan read as well as clearthis bit bywriting 0.Writing1'hasnoeffectonthebitvaluetoggle (t)Software can onlytoggle this bit by writing'1.Writingo'has no effect.Reserved (Res.)Reservedbit,mustbekeptatresetvalue.1.3About the STM32 Cortex-M3 processor and coreperipheralsTheCortex-M3processorisbuiltonahigh-performanceprocessorcore,witha3-stagepipelineHarvard architecture,making it idealfor demanding embeddedapplications.Theprocessordeliversexceptional powerefficiencythroughanefficientinstructionsetandextensively optimized design,providing high-end processinghardware including single-cycle32x32multiplicationanddedicatedhardwaredivision.A10/156DocID15491Rev6
About this document PM0056 10/156 DocID15491 Rev 6 1 About this document This document provides the information required for application and system-level software development. It does not provide information on debug components, features, or operation. This material is for microcontroller software and hardware engineers, including those who have no experience of Arm products. 1.1 Typographical conventions The typographical conventions used in this document are: 1.2 List of abbreviations for registers The following abbreviations are used in register descriptions: 1.3 About the STM32 Cortex®-M3 processor and core peripherals The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including singlecycle 32x32 multiplication and dedicated hardware division. italic Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. < and > Enclose replaceable terms for assembler syntax where they appear in code or code fragments. For example: LDRSB<cond> <Rt>, [<Rn>, #<offset>] read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value. read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit value. toggle (t) Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect. Reserved (Res.) Reserved bit, must be kept at reset value