O Active-HDL 4.2 (happy)-e: \MY_HDLdesi gn happy\src\HEX2LEDwhd File Edit Search View Design Simulation Tools Help e+》x Design Browser.x10 library IEEE use IEEE std logic 1164.all; Top-Level selection 3 entity HEXZLED is [B happy 14 port Add New File 15 HEX: in sTD LOGIC VECTOR (3 downto 0); 自?Hx2 LED. vhd 16 LED: out STD LOGIC VECTOR (6 downto 0) 中口 functional 17 MM happy library 18 end HEX2LED: 19 20 --)) End of automatically maintained section 22 architecture HEX2LED of HEX2 LED is <<enter your statements here>> 25 E hex 2led. hd o desi 15:30,2002年10月29日 Dease M3 UTI S6gcx31gxyr BFiles $St. GRe.9 Console Ready Ln 1. col 1
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esTc 设计中 FPGA Express
设计中心 FPGA Express
FRFPGA Express File View Help To begin designing with FPGA Express, create or open a project An FPGA Express project is defined by the EXP project file and a project folder 国国 Errors A Warner0M/ For Help, press F1
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ER FPGA Express-[studyl File Edit Synthesis Filters View Window Help ①学R|@息 invert To synthesize the design, select the top level design name from the drop down list Then choose the target FPGA device to synthesize a new design implementation Design Sources Chips 日 Sstudy +日WoRK KAE Errors Warnings A Messages For Help, press F1
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FPGA Express-[study] File Edit Synthesis Filters View Window Help ]D? src To synthesize the design,s Then choose the target FPGA文件()编辑g)查看)收藏)工具)帮助⑩) Design Sources 中后退,中国③搜乌文件夹④X2, 日 study 地址)□ 转到 +b invert.vhd and2. yhd and 3. vhd nd_2 d_3 d2 +band3.vhd src ± b tri_state.vhd +b dff.vhd 9个选定的项目。 +1 aaa. hd +b nor3.vhd 总计文件大小:4.313B design +b norwhd orT vhd invert full adder, yhd and 3 ± B invert_link.hd and2 full adder HCT175 nvert 选定9个对象 4313B巴我的电脑
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