iscussion of all unit step processes presented. Further details and more recent process developments can be found in several magazines/journals, such as Semiconductor International, Solid State Technology, IEEE Trans- actions on Semiconductor Manufacturing, IEEE Transactions on Electron Devices, IEEE Electron Device Letters, Journal of Applied Physics, and the Journal of the Electrochemical Society 23.2 Testing Wayne Needham The function of test of a semiconductor device is twofold first is design debug, to understand the failing section of the device, identify areas for changes and verify correct modes of operation. The second major area is to imply separate good devices from bad devices in a production test environment. Data collection and infor mation analysis are equally important in both types of test, but for different reasons. The first case is obvious, debug requires understanding of the part. In the second case, data collected from a test program may be used for yield enhancement. This is done by finding marginal areas of the device or in the fabrication process and then making improvements to raise yields and therefore lower cost. In this section, we will look at methods of testing which can be used for data collection, analysis, and debug of a new device. No discussion of test would be useful if the test strategy was not thought out clearly before design implementation. Design for test(access for control and observation) is a requirement for successful debug and testing of any semiconductor device The basis for all testing of complex integrated circuits is a comparison of known good patterns to the response of a dut ( device under test). The simulation of the devices is done with input stimuli, and those same input stimuli( vectors)are presented on the DUT. Comparisons are made cycle by cycle with an option to ignore certain pins, times, or patterns. If the device response and the expected response are not in agreement, the devices are usually considered defective This section will cover common techniques for testing. Details of generation of test programs, simulation of devices, and tester restrictions are not covered here. Built-In Self- Test Self-testing(built-in self-test or BIST) is essentially the implementation of logic built into the circuitry to do testing without the use of the tester for pattern generation and comparison purposes. a tester is still needed to categorize failures and to separate good from bad units. In this case the test system supplies clocks to the device and determines pass/fail from the outputs of the device. The sequential elements are run with a known data pattern, and a signature is generated. The signature can be a simple go or no-go signal presented on one pin of the part, or the signal may be a polynomial generated during testing. This polynomial has some significance to actual states of the part. Figure 23. 8 shows a typical self-testing technique implemented on a large block of random logic, inside a device. The number of unique inputs to the logic block should be limited to 20 bits so the total vectors are less than one million. This keeps test time to less than one second in most cases. Self-test capability can be implemented on virtually any size block. It is important to understand the tradeoffs between the extra logic added to implement self-testing and the inherent logic of the block to be tested. For instance, adding self-testing capability to a RAM requires adding counters and read, write, and multiplexor circuitry to allow access to the part. The access is needed not only by the self-test circuitry, but by the circuit that would normally acce When implementing self-testing on blocks such as RAMs and ROMs, it is worthwhile to note the typical failure mode of semiconductor devices. Single-bit defects can easily be detected using self-testing techniques ingle-point defects in the manufacturing process can show up as a single transistor failure in a RAM or ROM or they may be somewhat more complex. If a single-point defect happens to be in the decoder section or in a row or column within the RAM, a full section of the device may be nonfunctional. ions reproduced from W M. Needham, Designer's Guide to Testable ASIC Devices, New York: Van Nostrand Reinhold, 1991. With permission c2000 by CRC Press LLC
© 2000 by CRC Press LLC discussion of all unit step processes presented. Further details and more recent process developments can be found in several magazines/journals, such as Semiconductor International, Solid State Technology, IEEE Transactions on Semiconductor Manufacturing, IEEE Transactions on Electron Devices, IEEE Electron Device Letters, Journal of Applied Physics, and the Journal of the Electrochemical Society. 23.2 Testing1 Wayne Needham The function of test of a semiconductor device is twofold. First is design debug, to understand the failing section of the device, identify areas for changes and verify correct modes of operation. The second major area is to simply separate good devices from bad devices in a production test environment. Data collection and information analysis are equally important in both types of test, but for different reasons. The first case is obvious, debug requires understanding of the part. In the second case, data collected from a test program may be used for yield enhancement. This is done by finding marginal areas of the device or in the fabrication process and then making improvements to raise yields and therefore lower cost. In this section, we will look at methods of testing which can be used for data collection, analysis, and debug of a new device. No discussion of test would be useful if the test strategy was not thought out clearly before design implementation. Design for test (access for control and observation) is a requirement for successful debug and testing of any semiconductor device. The basis for all testing of complex integrated circuits is a comparison of known good patterns to the response of a DUT (device under test). The simulation of the devices is done with input stimuli, and those same input stimuli (vectors) are presented on the DUT. Comparisons are made cycle by cycle with an option to ignore certain pins, times, or patterns. If the device response and the expected response are not in agreement, the devices are usually considered defective. This section will cover common techniques for testing. Details of generation of test programs, simulation of devices, and tester restrictions are not covered here. Built-In Self-Test Self-testing (built-in self-test or BIST) is essentially the implementation of logic built into the circuitry to do testing without the use of the tester for pattern generation and comparison purposes. A tester is still needed to categorize failures and to separate good from bad units. In this case the test system supplies clocks to the device and determines pass/fail from the outputs of the device. The sequential elements are run with a known data pattern, and a signature is generated. The signature can be a simple go or no-go signal presented on one pin of the part, or the signal may be a polynomial generated during testing. This polynomial has some significance to actual states of the part. Figure 23.8 shows a typical self-testing technique implemented on a large block of random logic, inside a device. The number of unique inputs to the logic block should be limited to 20 bits so the total vectors are less than one million. This keeps test time to less than one second in most cases. Self-test capability can be implemented on virtually any size block. It is important to understand the tradeoffs between the extra logic added to implement self-testing and the inherent logic of the block to be tested. For instance, adding self-testing capability to a RAM requires adding counters and read, write, and multiplexor circuitry to allow access to the part. The access is needed not only by the self-test circuitry, but by the circuitry that would normally access the RAM. When implementing self-testing on blocks such as RAMs and ROMs, it is worthwhile to note the typical failure mode of semiconductor devices. Single-bit defects can easily be detected using self-testing techniques. Single-point defects in the manufacturing process can show up as a single transistor failure in a RAM or ROM, or they may be somewhat more complex. If a single-point defect happens to be in the decoder section or in a row or column within the RAM, a full section of the device may be nonfunctional. 1 Portions reproduced from W. M. Needham, Designer’s Guide to Testable ASIC Devices, New York: Van Nostrand Reinhold, 1991. With permission
Counter Latches FIGURE 23. 8 Example of self-test in circuit. SCLK FIGURE 23.9 Scan test implementati The problem with this failure mode is that RAMs and roms are typically laid out in a square or rectangula array. They are usually decoded in powers of 2, such as a 32*64 or a 256*512 array. If the self-testing circuitry is an 8-bit-wide counter or linear feedback shift register, there may be problems. There are 256 possible combinations within the states of the counter, and this may be a multiple of the row or columns. Notice that 256 possible rows or multiples of 256 rows in the array and 256 states in the counter make for a potential error masking combination. If the right type of failure modes occur and a full row is nonfunctional, it may be masked. The implementation of the counter or shift register must be done with full-column or row failure modes in mind, or it can easily mask failures. This masking of the failure gives a false result that the device is passing the test. Scan Scan is a test technique that ties together some or all the latches in the part to form a path through the part to shift data. Figure 23.9 shows the implementation of a scan latch in a circuit. Note that the latch has a dual mode of operation. In the normal mode the latches act like normal flip-flops for data storage. In the scan mode the latches act like a shift register connecting one element to another. This is a basic implementation of a shift c2000 by CRC Press LLC
© 2000 by CRC Press LLC The problem with this failure mode is that RAMs and ROMs are typically laid out in a square or rectangular array. They are usually decoded in powers of 2, such as a 32 * 64 or a 256 * 512 array. If the self-testing circuitry is an 8-bit-wide counter or linear feedback shift register, there may be problems. There are 256 possible combinations within the states of the counter, and this may be a multiple of the row or columns. Notice that 256 possible rows or multiples of 256 rows in the array and 256 states in the counter make for a potential errormasking combination. If the right type of failure modes occur and a full row is nonfunctional, it may be masked. The implementation of the counter or shift register must be done with full-column or row failure modes in mind, or it can easily mask failures. This masking of the failure gives a false result that the device is passing the test. Scan Scan is a test technique that ties together some or all the latches in the part to form a path through the part to shift data. Figure 23.9 shows the implementation of a scan latch in a circuit. Note that the latch has a dual mode of operation. In the normal mode the latches act like normal flip-flops for data storage. In the scan mode the latches act like a shift register connecting one element to another. This is a basic implementation of a shift FIGURE 23.8 Example of self-test in circuit. FIGURE 23.9 Scan test implementation. Block of logic In Out Counter Latches Combinatorial logic DI Q SI CLK SCLK DI Q SI CLK SCLK DI Q SI CLK SCLK
CLK CLK CLK SCLK SCLK SCLK I Out CLK FIGURE 23.10 Scan test example and patterns. register or scan latch in a block of logic. Data can be shifted in via the shift pin or can be clocked in from the data pin Clock line is the normal system clock and SCLK is the shift clock for scan operations. Data for testing is shifted in on the serial data in pins of the device. Patterns for the exercise of the combinatorial logic could be generated by truth table or by random generation of patterns. These patterns are then clocked a single time to store the results of the combinatorial logic. The latches now contain the results of the combinatorial logic operations. Testing of the logic becomes quite easy, as the sequential depth into the part is of no significance to the designer. Once the patterns are latched, the same serial technique is used to shift them out for comparison purposes. At the time of outward shift, new patterns are shifted in Figure 23.10 shows this pattern shift for a circuit using scan. This is the actual implementation of scan in a small group of logic including the truth table associated with it and one state of testing Direct Access Testing Direct access is a method whereby one gains access to a device logic to the outside world via multiplexors. Data is then forced into the block directly and the outputs are directly measured. This is one of the simplest methods to check devices for logic functionality. This particular method would supplement previous testing methods by allowing the user to impose data patterns directly on large blocks of logic. The same feature holds true for output observation. In the direct access scheme, access of a test mode would force certain logic blocks via multiplexors to have access to the outside pins of the part. One could then drive the data patterns to the input pins, compare output pins of the part, and measure the access, status, and logical functionality of the block directly. Figure 23 11 shows implementation of direct access test techniques on a block of logic. During normal operation, the logic block B has inputs driven by the logic block A, and outputs are connected to the logic block C In the test mode, the two multiplexors are switched so that the input and output pins of the device an control and observe the logic block B directly Joint Test Action Group TAG) When implemented in a device, JTAG (Joint Test Action Group), or IEEE 1149.1, allows rapid and accurate measurement of the direct connections from one device to another on a PC board. This specification defines c2000 by CRC Press LLC
© 2000 by CRC Press LLC register or scan latch in a block of logic. Data can be shifted in via the shift pin or can be clocked in from the data pin. Clock line is the normal system clock and SCLK is the shift clock for scan operations. Data for testing is shifted in on the serial data in pins of the device. Patterns for the exercise of the combinatorial logic could be generated by truth table or by random generation of patterns. These patterns are then clocked a single time to store the results of the combinatorial logic. The latches now contain the results of the combinatorial logic operations. Testing of the logic becomes quite easy, as the sequential depth into the part is of no significance to the designer. Once the patterns are latched, the same serial technique is used to shift them out for comparison purposes. At the time of outward shift, new patterns are shifted in. Figure 23.10 shows this pattern shift for a circuit using scan. This is the actual implementation of scan in a small group of logic including the truth table associated with it and one state of testing. Direct Access Testing Direct access is a method whereby one gains access to a device logic block by bringing signals from the block to the outside world via multiplexors. Data is then forced into the block directly and the outputs are directly measured. This is one of the simplest methods to check devices for logic functionality. This particular method would supplement previous testing methods by allowing the user to impose data patterns directly on large blocks of logic. The same feature holds true for output observation. In the direct access scheme, access of a test mode would force certain logic blocks via multiplexors to have access to the outside pins of the part. One could then drive the data patterns to the input pins, compare output pins of the part, and measure the access, status, and logical functionality of the block directly. Figure 23.11 shows implementation of direct access test techniques on a block of logic. During normal operation, the logic block B has inputs driven by the logic block A, and outputs are connected to the logic block C. In the test mode, the two multiplexors are switched so that the input and output pins of the device can control and observe the logic block B directly. Joint Test Action Group (JTAG) When implemented in a device, JTAG (Joint Test Action Group), or IEEE 1149.1, allows rapid and accurate measurement of the direct connections from one device to another on a PC board. This specification defines FIGURE 23.10 Scan test example and patterns. DI Q SI CLK SCLK DI Q SI CLK SCLK DI Q SI CLK SCLK Scan Data In In Out SCLK CLK 1 0 1 X 1 1 1 X X X X 0 0 1 1 1 1 0 1 1 1 0 0 0 1 0 0 0
Multiplexor Output FIGURE 23.11 Direct access implementation. nstruction Multiplexor TAP TDO TCK TMS FIGURE 23. 12 TAP circuit implementation a Test Access Port(TAP)for internal and external IC testing Figure 23. 12 shows the TAP use in a small device, thus allowing accurate measurement and detection of solder connections and bridging on a PC board. This technique allows the shifting of data through the input and output pins of the part to ensure correct connections on the PC board. The four required pins are shown at the bottom of the drawing, and all the i/o ports are modified to include 1149.1 latches. The internal logic of the part does not need to change in order to implement 1149.1 boundary scan capability. JTAG test capability, or IEEE P11491 standard Test Access Port and boundary scan capability, allows the designer to implement features that enhance testing. Both PC board test capability and the internal logic verification of the device can be facilitated. For systems where remaining components on the boards are implemented with the 1149. 1 scan approach, adding a TaP to a device is a wise step to take. Scan, BIST, and direct access can all be controlled by the 1149.1 test access port c2000 by CRC Press LLC
© 2000 by CRC Press LLC a Test Access Port (TAP) for internal and external IC testing. Figure 23.12 shows the TAP use in a small device, thus allowing accurate measurement and detection of solder connections and bridging on a PC board. This technique allows the shifting of data through the input and output pins of the part to ensure correct connections on the PC board. The four required pins are shown at the bottom of the drawing, and all the I/O ports are modified to include 1149.1 latches. The internal logic of the part does not need to change in order to implement 1149.1 boundary scan capability. JTAG test capability, or IEEE P1149.1 standard Test Access Port and boundary scan capability, allows the designer to implement features that enhance testing. Both PC board test capability and the internal logic verification of the device can be facilitated. For systems where remaining components on the boards are implemented with the 1149.1 scan approach, adding a TAP to a device is a wise step to take. Scan, BIST, and direct access can all be controlled by the 1149.1 test access port. FIGURE 23.11 Direct access implementation. FIGURE 23.12 TAP circuit implementation. Input pins Output pins Logic A Logic B Multiplexor Multiplexor Logic C
234 s678 Multiplex Test mode FIGURE 23 13 Typical patterns for function test. Pattern Generation for Functional Test Using Unit Delay During simulation of the function portion of the device, patterns are captured and stored for exercise of the system Figure 23 13 shows typical patterns for each block and the width of the data for test. The patterns check functionality of the logic and ensure that the logic implemented performs the desired function in the device The patterns can be generated by several methods if they were not generated by self-test. First is exercising of the system by use of code such as assemblers, macros, and high-level inputs that ensure the operation. Usually this is done by comparison of a high-level model to the actual logic. A second method of pattern generation is random number generation; in this case random numbers of ones and zeros are impressed on the logic and the results compared to a high-level model. Finally, coding of ones and zeros for logic checking is an alternative, but this is typically prohibitive in today's technology where devices may contain millions of logic gates. Pattern Generation for Timing After the functional patterns are complete, specific tests for timing may be generated. Timing tests are test procedures to verify the correction operation to the timing specification of the device. Typical timing tests include outputs relative to the clocks, propagation delays, set-up and hold times, access times, minimum and maximum speed of operation, rise and fall time, and others. These tests are captured in simulation and used in the test system to verify performance of the device. Table 23. 1 shows the relationship between time-based simulation and cycle-based test files. Temperature, Voltage, and Processing Effects Figure 23 14 shows the impact on speed of process variations, and as a result of voltage or temperature variations. It is important to simulate with the total variation over the entire process, temperature, and voltage range to ensure testability. Remember that if the system design of the logic was not done with some guardbanding, there may be no margin. If the library used for the design did not include some amount of margin, there may be a need to add guardbanding by optimizing logic for speed or choosing faster gates. There must be a delta placed c2000 by CRC Press LLC
© 2000 by CRC Press LLC Pattern Generation for Functional Test Using Unit Delay During simulation of the function portion of the device, patterns are captured and stored for exercise of the system. Figure 23.13 shows typical patterns for each block and the width of the data for test. The patterns check the functionality of the logic and ensure that the logic implemented performs the desired function in the device. The patterns can be generated by several methods if they were not generated by self-test. First is exercising of the system by use of code such as assemblers, macros, and high-level inputs that ensure the operation. Usually this is done by comparison of a high-level model to the actual logic. A second method of pattern generation is random number generation; in this case random numbers of ones and zeros are impressed on the logic and the results compared to a high-level model. Finally, coding of ones and zeros for logic checking is an alternative, but this is typically prohibitive in today’s technology where devices may contain millions of logic gates. Pattern Generation for Timing After the functional patterns are complete, specific tests for timing may be generated. Timing tests are test procedures to verify the correction operation to the timing specification of the device. Typical timing tests include outputs relative to the clocks, propagation delays, set-up and hold times, access times, minimum and maximum speed of operation, rise and fall time, and others. These tests are captured in simulation and used in the test system to verify performance of the device. Table 23.1 shows the relationship between time-based simulation and cycle-based test files. Temperature, Voltage, and Processing Effects Figure 23.14 shows the impact on speed of process variations, and as a result of voltage or temperature variations. It is important to simulate with the total variation over the entire process, temperature, and voltage range to ensure testability. Remember that if the system design of the logic was not done with some guardbanding, there may be no margin. If the library used for the design did not include some amount of margin, there may be a need to add guardbanding by optimizing logic for speed or choosing faster gates. There must be a delta placed FIGURE 23.13 Typical patterns for function test. Block A Block B Block C Block D Multiplexor Multiplexor Test Mode Block Width Pattern Sets 1 2 3 4 5 6 7 8 9 10 4 12 16 6 A B C D