Lattice Damage and annealing During ion implantation the impinging atoms can displace Si atoms in the lattice, causing damage to the crystal For high implant doses the damage can be severe enough to make the implanted region amorphous. Typicall light ions, or light doses of heavy ions, will cause primary crystalline defects(interstitials and vacancies), whereas medium to heavy doses of heavy ions will cause amorphous layers. Implant damage can be removed by annealing the wafers in an inert gas at 800 to 1000.C for approximately 30 minutes. Annealing cycles at high temperatures can cause appreciable diffusion which must be considered, especially in the newer technologies where shallow junctions are required. Rapid thermal annealing(rTA) can be successfully applied to prevent undesirable diffusion in these cases Wolf and Tauber, 1986 eposition During IC fabrication, thin films of dielectrics(SiO2, Si Na, etc. ) polysilicon, and metal conductors are deposited on the wafer surface to form devices and circuits. The techniques used for forming these thin films are physical vapor deposition(PVD), chemical vapor deposition(CVD), and epitaxy, which is just a special case of CVD Physical Vapor Deposition Vacuum evaporation and sputtering are the two methods of physical vapor deposition used in the fabrication of integrated circuits. Both of these processes are carried out in a vacuum to prevent contamination of the substrate and to provide a reasonable mean free path for the material being deposited. In the early days of integrated circuits aluminum was used exclusively for IC metallization and evaporation was used for its deposition As IC technology matured, the need for metal alloys, alternative metals, and various insulating thin films stimulated the development and acceptance of sputter deposition as the Pvd method of choic When the temperature is raised high enough to melt a solid some of the atoms have enough internal energy to break the surface and escape into the surrounding atmosphere. These evaporated atoms strike the wafer and condense into a thin film. Typical film thickness used in the IC industry are in the few thousand angstroms to um range. Heat is provided by resistance heating, electron beam heating, or by rf inductive heating. Discussions of these techniques and their historical significance can be found in most processing books [e.g., Sze, 1983 Wolf and Tauber, 1986]. The most commonly used system employs a focussed electron beam scanned over a crucible of metal as illustrated in Fig 23. 6(a). Contamination levels can be quite low because only electrons come in contact with the melted metal. A high intensity electron beam, typically 15 keV, bent through a 270 gle to shield the wafers from filament contamination, provides the heating for evaporation of the metal. The wafers are mounted above the source on a planetary substrate holder tha und the source during the deposition to insure uniform step coverage. For the planetary substrate holder, shown schematically in Fig 23.6(b), the growth rate is independent of substrate position. The relatively large size of the crucible provide an ample supply of source material for the depositions. The deposition rate is controlled by changing the current and energy of the electron beam. Dual beams with dual targets can be used to coevaporate composite films. Device degradation due to X-ray radiation, generated by the electron beam system, is of great concern in MOS processing. Because of this, sputtering has replaced e-beam evaporation in many process lines Sputtering is accomplished by bombarding a target surface with energetic ions that dislodge target atoms from the surface by direct momentum transfer. Under proper conditions the sputtered atoms are transported to the wafer surface where they deposit to form a thin film. Sputter deposition takes place in a chamber that is evacuated and then backfilled with an inert gas at roughly 10 mtorr pressure. a glow discharge between two electrodes, one of which is the target, within the gas creates a plasma that provides the source of ions for the sputter process. Metals can be sputtered in a simple dc parallel plate reactor with the most negative electrode being the target and the most positive electrode(usually ground) being the substrate holder. If the dc voltage is replaced by an rf voltage, insulators as well as conductors can be sputter deposited. Magnetron systems incorporate a magnetic field that enhances the efficiency of the discharge by trapping secondary electrons in lowers substrate heating by reducing the energy of electrons reaching the wafer. Circular magnetrons(or S-guns) virtually eliminate substrate heating by electron bombardment due to a ring-shaped cathode/anode combination with the substrate a nonparticipating system electrode [Sze, 1983]. Besides insu lators and conductors, sputtering can be used to deposit alloy films with the same composition as an alloy target. c2000 by CRC Press LLC
© 2000 by CRC Press LLC Lattice Damage and Annealing During ion implantation the impinging atoms can displace Si atoms in the lattice, causing damage to the crystal. For high implant doses the damage can be severe enough to make the implanted region amorphous. Typically, light ions, or light doses of heavy ions,will cause primary crystalline defects (interstitials and vacancies), whereas medium to heavy doses of heavy ions will cause amorphous layers. Implant damage can be removed by annealing the wafers in an inert gas at 800 to 1000°C for approximately 30 minutes. Annealing cycles at high temperatures can cause appreciable diffusion which must be considered, especially in the newer technologies where shallow junctions are required. Rapid thermal annealing (RTA) can be successfully applied to prevent undesirable diffusion in these cases [Wolf and Tauber, 1986]. Deposition During IC fabrication, thin films of dielectrics (SiO2, Si3N4, etc.), polysilicon, and metal conductors are deposited on the wafer surface to form devices and circuits. The techniques used for forming these thin films are physical vapor deposition (PVD), chemical vapor deposition (CVD), and epitaxy, which is just a special case of CVD. Physical Vapor Deposition Vacuum evaporation and sputtering are the two methods of physical vapor deposition used in the fabrication of integrated circuits. Both of these processes are carried out in a vacuum to prevent contamination of the substrate and to provide a reasonable mean free path for the material being deposited. In the early days of integrated circuits aluminum was used exclusively for IC metallization and evaporation was used for its deposition. As IC technology matured, the need for metal alloys, alternative metals, and various insulating thin films stimulated the development and acceptance of sputter deposition as the PVD method of choice. When the temperature is raised high enough to melt a solid some of the atoms have enough internal energy to break the surface and escape into the surrounding atmosphere. These evaporated atoms strike the wafer and condense into a thin film. Typical film thickness used in the IC industry are in the few thousand angstroms to 1 mm range.Heat is provided by resistance heating, electron beam heating, or by rf inductive heating. Discussions of these techniques and their historical significance can be found in most processing books [e.g., Sze, 1983; Wolf and Tauber, 1986]. The most commonly used system employs a focussed electron beam scanned over a crucible of metal as illustrated in Fig. 23.6(a). Contamination levels can be quite low because only electrons come in contact with the melted metal. A high intensity electron beam, typically 15 keV, bent through a 270° angle to shield the wafers from filament contamination, provides the heating for evaporation of the metal. The wafers are mounted above the source on a planetary substrate holder that rotates around the source during the deposition to insure uniform step coverage. For the planetary substrate holder, shown schematically in Fig. 23.6(b), the growth rate is independent of substrate position. The relatively large size of the crucible provides an ample supply of source material for the depositions. The deposition rate is controlled by changing the current and energy of the electron beam. Dual beams with dual targets can be used to coevaporate composite films. Device degradation due to X-ray radiation, generated by the electron beam system, is of great concern in MOS processing. Because of this, sputtering has replaced e-beam evaporation in many process lines. Sputtering is accomplished by bombarding a target surface with energetic ions that dislodge target atoms from the surface by direct momentum transfer. Under proper conditions the sputtered atoms are transported to the wafer surface where they deposit to form a thin film. Sputter deposition takes place in a chamber that is evacuated and then backfilled with an inert gas at roughly 10 mtorr pressure. A glow discharge between two electrodes, one of which is the target, within the gas creates a plasma that provides the source of ions for the sputter process. Metals can be sputtered in a simple dc parallel plate reactor with the most negative electrode being the target and the most positive electrode (usually ground) being the substrate holder. If the dc voltage is replaced by an rf voltage, insulators as well as conductors can be sputter deposited. Magnetron systems incorporate a magnetic field that enhances the efficiency of the discharge by trapping secondary electrons in the plasma and lowers substrate heating by reducing the energy of electrons reaching the wafer. Circular magnetrons (or S-guns) virtually eliminate substrate heating by electron bombardment due to a ring-shaped cathode/anode combination with the substrate a nonparticipating system electrode [Sze, 1983]. Besides insulators and conductors, sputtering can be used to deposit alloy films with the same composition as an alloy target
Al charge ler cooled FIGURE 23.6(a)Electron beam evaporation source (b) Geometry for a planetary holder. Chemical Vapor Deposition Chemical vapor deposition(CVD)is a method of Growth ra Surface Reaction forming thin films on a substrate in which energy is Limited Regio supplied for a gas phase reaction. The energy may be at tion. Since the reaction can take place close to the substrate, CVD can be performed at atmospheric 2 Relatively high temperatures can be used, resulting in s k,, exp-EA们 excellent conformal step coverage, or relatively low be perature film such as aluminum Substrates can of Si is simply CVD on a single crystalline substrate FIGURE 23.7 Typical chemical vapor deposition growth resulting in single crystal layer. Generally, unless the rate versus reciprocal temperature characteristics. qualifying adjective epitaxial is used, the depositions are assumed to result in amorphous or polycrystalline films. Typically all CvD depositions show a growth rate versus temperature dependence as illustrated in Fig. 23.7. At low temperatures the deposition is surface reaction rate limited and shows an Arrhenius type behavior At high temperatures the rate is dominated by mass transfer of the reactant and growth rate is essentially temperature independent. The transition temperature where the reaction switches from reaction rate to mass flow dominated is dependent on other factors such as pressur reactant species, and energy source. several types of films can be deposited by CVD Insulators and dielectrics(such as SiO2 and Si,N4), doped glasses(PSG, BPSG), and nonstoichiometric dielectrics as well as semiconductors(such as Si, Ge, GaAs, and GaP)can be deposited Conductors of pure metals, such as Al, Ni, Au, Pt, Ti, etc, as well as silicides such as WSi, and MoSi, can also be deposited c2000 by CRC Press LLC
© 2000 by CRC Press LLC Chemical Vapor Deposition Chemical vapor deposition (CVD) is a method of forming thin films on a substrate in which energy is supplied for a gas phase reaction. The energy may be supplied by heat, plasma excitation, or optical excitation. Since the reaction can take place close to the substrate, CVD can be performed at atmospheric pressure (i.e., low mean free path) or at low pressures. Relatively high temperatures can be used, resulting in excellent conformal step coverage, or relatively low temperatures can be used to passivate a low melting temperature film such as aluminum. Substrates can be amorphous or single crystalline. Epitaxial growth of Si is simply CVD on a single crystalline substrate resulting in single crystal layer. Generally, unless the qualifying adjective epitaxial is used, the depositions are assumed to result in amorphous or polycrystalline films. Typically all CVD depositions show a growth rate versus temperature dependence as illustrated in Fig. 23.7. At low temperatures the deposition is surface reaction rate limited and shows an Arrhenius type behavior. At high temperatures the rate is dominated by mass transfer of the reactant and growth rate is essentially temperature independent. The transition temperature where the reaction switches from reaction rate to mass flow dominated is dependent on other factors such as pressure, reactant species, and energy source. Several types of films can be deposited by CVD. Insulators and dielectrics (such as SiO2 and Si3N4), doped glasses (PSG, BPSG), and nonstoichiometric dielectrics as well as semiconductors (such as Si, Ge, GaAs, and GaP) can be deposited. Conductors of pure metals, such as Al, Ni, Au, Pt, Ti, etc., as well as silicides such as WSi2 and MoSi2 can also be deposited. FIGURE 23.6 (a) Electron beam evaporation source. (b) Geometry for a planetary holder. Source Wafer Normal to surface Vapor stream Al charge Water cooled Cu hearth e beam (a) (b) q q ro ro ro o FIGURE 23.7 Typical chemical vapor deposition growth rate versus reciprocal temperature characteristics
CVD systems come in a multitude of designs and configurations and are selected for the compatibility with method, energy source, and temperature range being used. Reaction chambers can be quartz, similar to diffusion r oxidation furnaces, or stainless steel Wafer holders also depend on the type of reaction and can be graphite, quartz, or stainless steel Cold wall systems employ direct heating of the substrate or wafer holder by induction or radiation. As such, the reaction takes place right at the wafer surface and is usually cleaner because the film does not build up on the chamber walls. In a hot wall deposition system the reaction takes place in the gas stream and the reaction product is deposited on every surface in the system, including the walls. Such unwanted depositions build up and flake off of these surfaces in time. Without proper cleaning and maintenance proce dures they become a source of contamination. Atmospheric deposition systems were first used in the deposition of epitaxial Si in bipolar processes(i.e buried layer formation). Early systems were horizontal rf induction heated systems using graphite substrate holders. Atmospheric pressure systems rely on flow dynamics in the chamber to produce uniform films. Since the reactant species is being depleted from the gas stream, it is imperative that the system design(flow pattern and rate)ensure that all wafers receive the same amount of deposit. Because of this, most atmospheric depositions are carried out using a horizontal or near horizontal wafer holder. Low-pressure CVD depositions are done at pressures in the 0.5 to l torr range and most often in a horizontal hot wall reactor. Wafers are held vertically and the system is operated in the reaction rate limited regime. A multi-zone furnace(typically three) is used to allow the temperature to be increased along the wafer holder to compensate for gas depletion by the deposition along the flow path. LPCVD is typically used to deposit Sio (925"C), Si,N4(=850C), and polycrystalline Si(=630.C). Due to the higher temperatures excellent conformal tep coverage can be obtained. Plasma-enhanced CVD uses a plasma to supply the required reaction energy. Typically, rf energy is used to produce a glow discharge such that the gas constituents are in a highly reactive state. Because of the ability of the plasma to impart high energy to the reaction at low temperature, these depositions maintain many of the excellent features of LPCVD, such as step coverage, with low temperature attributes, such as reduced waf warpage, less impurity diffusion, and less film stress Plasma-enhanced de highly hydrogenated films such as SiO-H, SiN-H, and amorphous S-l position results in nonstoichiometric Lithography and Pattern Transfer In the production of integrated circuits various thin films are fabricated in the Si wafer or grown or deposited on the surface. Each of these layers has a functionality as either an active part of a device, a barrier or mask, or an inter-or intra-layer isolation. To perform its intended function, each of these layers has to be located in specific regions on the wafer surface. This is accomplished by either patterning and etching a thin film to serve a mask to form the desired function by a blanket process or by forming the desired layer and then patterning and etching it to provide the device function in local area Wafer Patterning Lithography is a transfer process where the pattern on a mask is replicated in a radiation-sensitive layer on the wafer surface. Typically, this has been accomplished with UV light as the radiation source and photoresist, or resist in conventional terminology, which is a UV-sensitive polymer, as the mask layer. The wafers with the layer to be patterned are cleaned and prebaked(400-800oC for 20-30 min) to drive off moisture and promot point, which functions by removing unwanted surface radicals that prevent adhesion. Then, a few drops of resist are deposited on a wafer which is spinning at a slow rate to produce a uniform coating and the spin speed is increased to enhance drying. The wafer with resist is softbaked at 80-90 C for 10-30 min to drive off the remaining solvents. The wafers are then put in an exposure system and the mask pattern to be transferred is aligned to any existing wafer patterns. Present-day exposure systems are step and repeat cameras where the mask is a 5-10x enlargement of a single chip pattern. Earlier systems used a 1x mask for the whole wafer and were of the contact, proximity, or Ix projection variety [Anner, 1990]. The resist is exposed through the mask to UV radiation that changes its structure, depending on whether the resist type is positive or negative. Negative c2000 by CRC Press LLC
© 2000 by CRC Press LLC CVD systems come in a multitude of designs and configurations and are selected for the compatibility with method, energy source, and temperature range being used. Reaction chambers can be quartz, similar to diffusion or oxidation furnaces, or stainless steel. Wafer holders also depend on the type of reaction and can be graphite, quartz, or stainless steel. Cold wall systems employ direct heating of the substrate or wafer holder by induction or radiation. As such, the reaction takes place right at the wafer surface and is usually cleaner because the film does not build up on the chamber walls. In a hot wall deposition system the reaction takes place in the gas stream and the reaction product is deposited on every surface in the system, including the walls. Such unwanted depositions build up and flake off of these surfaces in time. Without proper cleaning and maintenance procedures they become a source of contamination. Atmospheric deposition systems were first used in the deposition of epitaxial Si in bipolar processes (i.e., buried layer formation). Early systems were horizontal rf induction heated systems using graphite substrate holders. Atmospheric pressure systems rely on flow dynamics in the chamber to produce uniform films. Since the reactant species is being depleted from the gas stream, it is imperative that the system design (flow pattern and rate) ensure that all wafers receive the same amount of deposit. Because of this, most atmospheric depositions are carried out using a horizontal or near horizontal wafer holder. Low-pressure CVD depositions are done at pressures in the 0.5 to 1 torr range and most often in a horizontal hot wall reactor. Wafers are held vertically and the system is operated in the reaction rate limited regime. A multi-zone furnace (typically three) is used to allow the temperature to be increased along the wafer holder to compensate for gas depletion by the deposition along the flow path. LPCVD is typically used to deposit SiO2 (ª925°C), Si3N4 (ª850°C), and polycrystalline Si (ª630°C). Due to the higher temperatures excellent conformal step coverage can be obtained. Plasma-enhanced CVD uses a plasma to supply the required reaction energy. Typically, rf energy is used to produce a glow discharge such that the gas constituents are in a highly reactive state. Because of the ability of the plasma to impart high energy to the reaction at low temperature, these depositions maintain many of the excellent features of LPCVD, such as step coverage, with low temperature attributes, such as reduced wafer warpage, less impurity diffusion, and less film stress. Plasma-enhanced deposition results in nonstoichiometric highly hydrogenated films such as SiO-H, SiN-H, and amorphous Si-H. Lithography and Pattern Transfer In the production of integrated circuits various thin films are fabricated in the Si wafer or grown or deposited on the surface. Each of these layers has a functionality as either an active part of a device, a barrier or mask, or an inter- or intra-layer isolation. To perform its intended function, each of these layers has to be located in specific regions on the wafer surface. This is accomplished by either patterning and etching a thin film to serve as a mask to form the desired function by a blanket process or by forming the desired layer and then patterning and etching it to provide the device function in local areas. Wafer Patterning Lithography is a transfer process where the pattern on a mask is replicated in a radiation-sensitive layer on the wafer surface. Typically, this has been accomplished with UV light as the radiation source and photoresist, or resist in conventional terminology, which is a UV-sensitive polymer, as the mask layer. The wafers with the layer to be patterned are cleaned and prebaked (400–800°C for 20–30 min) to drive off moisture and promote resist adhesion. Many processes also add an adhesion promoter, such as hexamethydisilazane (HMDS), at this point, which functions by removing unwanted surface radicals that prevent adhesion. Then, a few drops of resist are deposited on a wafer which is spinning at a slow rate to produce a uniform coating and the spin speed is increased to enhance drying. The wafer with resist is softbaked at 80–90°C for 10–30 min to drive off the remaining solvents. The wafers are then put in an exposure system and the mask pattern to be transferred is aligned to any existing wafer patterns. Present-day exposure systems are step and repeat cameras where the mask is a 5–10¥ enlargement of a single chip pattern. Earlier systems used a 1¥ mask for the whole wafer and were of the contact, proximity, or 1¥ projection variety [Anner, 1990]. The resist is exposed through the mask to UV radiation that changes its structure, depending on whether the resist type is positive or negative. Negative
resist becomes polymerized (i. e, cross linked) in areas exposed to the radiation, whereas in a positive resist the polymer bonds are scissioned upon exposure. The resist is not affected in regions where the mask is opaque either case. After full wafer exposure the resist is developed such that the unpolymerized regions are selectively dissolved in an appropriate solvent. The polymerized portion of the resist remains intact on the wafer surface, replicating the opaque features of the mask in a positive resist and just the opposite for a negative resist. As the minimum feature size approaches the wavelength of light used in optical exposure systems(=4000 A), resolution is lost due to diffraction limitations. Alternatives are being developed to overcome these limita ons[Okazaki, 1991, the simplest of which is using shorter wavelength, i.e., deep UV, radiation to reduce the diffraction limit. A further extension of this technique introduces optical phase shifting in the photomask itself to extend the diffraction limit even further. These techniques are eventually limited, somewhere in the range of 2000 A, and alternative techniques such as electron beam or X-ray radiation will have to replace the UV radiation source. These techniques are quite analogous to UV systems but use resist specifically tailored for sensitivity in their appropriate wavelength range. Pattern Transfer After the resist pattern is formed it is then transferred to the surface layer of the wafer. Sometimes this is an invisible transfer, such as ion implantation, but more often than not it is a physical transfer of the pattern by etching the surface layer, using the resist as a mask. This results in the desired structure or produces a more etch-resistant mask for further pattern transfer operations Historically, the most common etch processes used wet chemicals. During wet etching, wafers with resist (or a resist transferred mask) are immersed in a temperature-controlled etchant for a fixed period of time. The etch rate is dependent on the strength of the etchant, temperature, and material being etched. Such chemical etches are isotopic, which means the vertical and lateral etch rates are the same. Thus, the thicker the layer being etched, the more undercutting of the mask pattern. Most wet etches are stopped with an underlying etchstop layer that is impervious to the etchant used to remove the top layer. In order to ensure the layer is totally removed, an over etch is allowed, which exacerbates the undercutting Modern high-density, small-feature processes require anisotropic etch processes; this requirement has driven the development of dry etching techniques. Plasma etching is a dry etch technique that uses an rf plasma to generate chemically active etchants that form volatile etch species with the substrate. Typically chlorine luorine compounds, most notably being CCl, and CFa, have been tailored for etching polysilicon, SiO2 Si,N, and metals. The etch rate can be significantly enhanced by adding 5-10%O2 to the etch gas. This, however, increases erosion of resist masks Early plasma etch systems were barrel reactors which used a perforated metal cylinder to confine the plasma in a region exterior to the wafers. In such reactors the etch species are electrically neutral so the reaction is entirely chemical and just as isotropic as wet chemical etch. A similar result occurs for a planar parallel plate rf reactor where the wafer is placed on the grounded electrode. However, some anisotropic etching is achieved this configuration because ions can reach the wafer. This is further enhanced in reactive ion etching(rIe) where the wafer is placed on the rf electrode in a planar parallel plate reactor. Here the ions experience a considerable acceleration to the wafer by the dc potential developed between plasma and cathode that results in anisotropic etching. The etch processes require significant characterization and development through opti mization of pressure, gas flow rate, gas mixture, and power to produce the desired etch rate, anisotropy, selectivity, uniformity and resist erosion. Nevertheless, this has become the etch process of choice in modern ULSI processes. A less popular version uses a beam of reactive species for the etch process and is called reactive ion beam etching(RIBe). Finally, it should be noted that near total anisotropic dry etching can be achieved with ion etching. This is done with an inactive species(e.g, Ar ions)either in a beam or with a parallel plate sputtering system with the wafer on the rf electrode. This results in an etch process that is entirely physical through momentum transfer. The etch rate is primarily controlled by the sputtering efficiency for various materials and thus does not differ significantly from material to material. Hence, such processes suffer from poor selectivity. Resist or mask erosion is also a problem with these techniques. Because of these limitations, virtually the only application of pure ion etching in VLSI/ULSI is for sputter cleaning of wafers before deposition c2000 by CRC Press LLC
© 2000 by CRC Press LLC resist becomes polymerized (i.e., cross linked) in areas exposed to the radiation, whereas in a positive resist the polymer bonds are scissioned upon exposure. The resist is not affected in regions where the mask is opaque in either case.After full wafer exposure the resist is developed such that the unpolymerized regions are selectively dissolved in an appropriate solvent. The polymerized portion of the resist remains intact on the wafer surface, replicating the opaque features of the mask in a positive resist and just the opposite for a negative resist. As the minimum feature size approaches the wavelength of light used in optical exposure systems (ª4000 Å), resolution is lost due to diffraction limitations. Alternatives are being developed to overcome these limitations [Okazaki, 1991], the simplest of which is using shorter wavelength, i.e., deep UV, radiation to reduce the diffraction limit. A further extension of this technique introduces optical phase shifting in the photomask itself to extend the diffraction limit even further. These techniques are eventually limited, somewhere in the range of 2000 Å, and alternative techniques such as electron beam or X-ray radiation will have to replace the UV radiation source. These techniques are quite analogous to UV systems but use resist specifically tailored for sensitivity in their appropriate wavelength range. Pattern Transfer After the resist pattern is formed it is then transferred to the surface layer of the wafer. Sometimes this is an invisible transfer, such as ion implantation, but more often than not it is a physical transfer of the pattern by etching the surface layer, using the resist as a mask. This results in the desired structure or produces a more etch-resistant mask for further pattern transfer operations. Historically, the most common etch processes used wet chemicals. During wet etching, wafers with resist (or a resist transferred mask) are immersed in a temperature-controlled etchant for a fixed period of time. The etch rate is dependent on the strength of the etchant, temperature, and material being etched. Such chemical etches are isotopic, which means the vertical and lateral etch rates are the same. Thus, the thicker the layer being etched, the more undercutting of the mask pattern. Most wet etches are stopped with an underlying etchstop layer that is impervious to the etchant used to remove the top layer. In order to ensure the layer is totally removed, an over etch is allowed, which exacerbates the undercutting. Modern high-density, small-feature processes require anisotropic etch processes; this requirement has driven the development of dry etching techniques. Plasma etching is a dry etch technique that uses an rf plasma to generate chemically active etchants that form volatile etch species with the substrate. Typically chlorine or fluorine compounds, most notably being CCl4 and CF4, have been tailored for etching polysilicon, SiO2, Si3N4, and metals. The etch rate can be significantly enhanced by adding 5–10% O2 to the etch gas. This, however, increases erosion of resist masks. Early plasma etch systems were barrel reactors which used a perforated metal cylinder to confine the plasma in a region exterior to the wafers. In such reactors the etch species are electrically neutral so the reaction is entirely chemical and just as isotropic as wet chemical etch. A similar result occurs for a planar parallel plate rf reactor where the wafer is placed on the grounded electrode. However, some anisotropic etching is achieved in this configuration because ions can reach the wafer. This is further enhanced in reactive ion etching (RIE) where the wafer is placed on the rf electrode in a planar parallel plate reactor. Here the ions experience a considerable acceleration to the wafer by the dc potential developed between plasma and cathode that results in anisotropic etching. The etch processes require significant characterization and development through optimization of pressure, gas flow rate, gas mixture, and power to produce the desired etch rate, anisotropy, selectivity, uniformity and resist erosion. Nevertheless, this has become the etch process of choice in modern ULSI processes. A less popular version uses a beam of reactive species for the etch process and is called reactive ion beam etching (RIBE). Finally, it should be noted that near total anisotropic dry etching can be achieved with ion etching. This is done with an inactive species (e.g., Ar ions) either in a beam or with a parallel plate sputtering system with the wafer on the rf electrode. This results in an etch process that is entirely physical through momentum transfer. The etch rate is primarily controlled by the sputtering efficiency for various materials and thus does not differ significantly from material to material. Hence, such processes suffer from poor selectivity. Resist or mask erosion is also a problem with these techniques. Because of these limitations, virtually the only application of pure ion etching in VLSI/ULSI is for sputter cleaning of wafers before deposition
Defining Terms Chemical vapor deposition: A process in which insulating or conducting films are depe on a substrate by use of reactant gases and an energy source to produce a gas-phase chemical reaction. The energy source may be thermal, optical, or plasma in nature in operation in which a film is placed on a wafer surface, usually without a chemical reactio with the underlying layer. Diffusion: A high-temperature process in which impurities on or in a wafer are redistributed within the silicon. If the impurities are desired dopants, this technique is often used to form specific device structures If the impurities are undesired contaminants, diffusion often results in undesired device degradation Dry etching: Processes that use gas-Phase reactants, inert or active ionic species, or a mixture of these to remove unprotected layers of a substrate by chemical processes, physical processes, or a mixture of these respectively. Ion implantation: A high-energy process, usually greater than 10 keV, that injects ionized species into a semiconductor substrate. Often done for introducing dopants for device fabrication into silicon with boron, phosphorus, or arsenic ions. Lithography: A patterning process in which a mask pattern is transferred by a radiation source to a radiatie sensitive coating that covers the substrate Physical vapor deposition: A process in which a conductive or insulating film is deposited on a wafer surface without the assistance of a chemical reaction. Examples are vacuum evaporation and sputtering Thermal oxidation of silicon: A high-temperature chemical reaction, typically greater than 800%C, in which the silicon of the wafer surface reacts with oxygen or water vapor to form silicon dioxin Wet etching: A process that uses liquid chemical reactions with unprotected regions of a wafer to remove of the substrate Related Topics 13. 1 Analog Circuit Simulation. 22. 1 Physical Properties References G.E. Anner, Planar Processing Primer, New York: Van Nostrand Reinhold, 1990 C.Y. Chang and S.M. Sze, ULSI Technology, New York: McGraw-Hill, 1995 B. Ciciani, Manufacturing Yield of VLSI, IEEE Press, 1995 S K. Ghandhi, The Theory and Practice of Microelectronics, New York: John Wiley Sons, 1968. S.K. Ghandhi, VLSI Fabrication Principles--Silicon and Gallium Arsenide, New York: John Wiley Sons, 1982. J.E.Gibbons, W.S. Johnson, and S M. Mylroie, Projected range statistics, in Semiconductors and Related Materials, ol. 2, 2nd ed, Dowden, Hutchinson, and Ross, Eds, New York: Academic Press, 197 A S Grove, Physics and Technology of Semiconductor Devices, New York: John Wiley Sons, 1967 IEEE Symposium on Semiconductor Manufacturing, IEEE Press, 1995 R C. Jaeger, Introduction to Microelectronic Fabrication, vol. 5 in the Modular Series on Solid State Devices, G W. Neudek and R.E. Pierret, Eds, Reading, Mass.: Addison-Wesley, 1988 S Okazaki,"Lithographic technology for future ULSI's, Solid State Technology, vol 34, no. 11, P. 77, November 1991 S M. Sze, Ed, VLSI Technology 2nd ed, New York: McGraw-Hill, 1988 P Van Zant, Microchip Fal on, 3rd ed. McGraw-Hill. 1996. S Wolf and R.N. Taube on Processing for the VLSI ERA, vol. 1, Process Technology, Sunset Beach, Calif: Lattice Press, 1986 Further Information The references given in this section have been chosen to provide more detail than is possible to provide in the limited space allocation for this section. Specifically, the referenced processing textbooks provide detail c2000 by CRC Press LLC
© 2000 by CRC Press LLC Defining Terms Chemical vapor deposition: A process in which insulating or conducting films are deposited on a substrate by use of reactant gases and an energy source to produce a gas-phase chemical reaction. The energy source may be thermal, optical, or plasma in nature. Deposition: An operation in which a film is placed on a wafer surface, usually without a chemical reaction with the underlying layer. Diffusion: A high-temperature process in which impurities on or in a wafer are redistributed within the silicon. If the impurities are desired dopants, this technique is often used to form specific device structures. If the impurities are undesired contaminants, diffusion often results in undesired device degradation. Dry etching: Processes that use gas-phase reactants, inert or active ionic species, or a mixture of these to remove unprotected layers of a substrate by chemical processes, physical processes, or a mixture of these, respectively. Ion implantation: A high-energy process, usually greater than 10 keV, that injects ionized species into a semiconductor substrate. Often done for introducing dopants for device fabrication into silicon with boron, phosphorus, or arsenic ions. Lithography: A patterning process in which a mask pattern is transferred by a radiation source to a radiationsensitive coating that covers the substrate. Physical vapor deposition: A process in which a conductive or insulating film is deposited on a wafer surface without the assistance of a chemical reaction. Examples are vacuum evaporation and sputtering. Thermal oxidation of silicon: A high-temperature chemical reaction, typically greater than 800°C, in which the silicon of the wafer surface reacts with oxygen or water vapor to form silicon dioxide. Wet etching: A process that uses liquid chemical reactions with unprotected regions of a wafer to remove specific layers of the substrate. Related Topics 13.1 Analog Circuit Simulation • 22.1 Physical Properties References G.E. Anner, Planar Processing Primer, New York: Van Nostrand Reinhold, 1990. C.Y. Chang and S.M. Sze, ULSI Technology, New York: McGraw-Hill, 1995. B. Ciciani, Manufacturing Yield of VLSI, IEEE Press, 1995. S.K. Ghandhi, The Theory and Practice of Microelectronics, New York: John Wiley & Sons, 1968. S.K. Ghandhi, VLSI Fabrication Principles—Silicon and Gallium Arsenide, New York: John Wiley & Sons, 1982. J.F. Gibbons, W.S. Johnson, and S.M. Mylroie, Projected range statistics, in Semiconductors and Related Materials, vol. 2, 2nd ed., Dowden, Hutchinson, and Ross, Eds., New York: Academic Press, 1975. A.S. Grove, Physics and Technology of Semiconductor Devices, New York: John Wiley & Sons, 1967. IEEE Symposium on Semiconductor Manufacturing, IEEE Press, 1995. R.C. Jaeger, Introduction to Microelectronic Fabrication, vol. 5 in the Modular Series on Solid State Devices, G.W. Neudek and R.F. Pierret, Eds., Reading, Mass.: Addison-Wesley, 1988. S. Okazaki, “Lithographic technology for future ULSI’s,” Solid State Technology, vol. 34, no. 11, p. 77, November 1991. S.M. Sze, Ed., VLSI Technology, 2nd ed., New York: McGraw-Hill, 1988. P. Van Zant, Microchip Fabrication, 3rd ed., McGraw-Hill, 1996. S. Wolf and R.N. Tauber, Silicon Processing for the VLSI ERA, vol. 1, Process Technology, Sunset Beach, Calif.: Lattice Press, 1986. Further Information The references given in this section have been chosen to provide more detail than is possible to provide in the limited space allocation for this section. Specifically, the referenced processing textbooks provide detailed