Electrical behavior of cmos Steady-state behavior when output is hold on 1 or o Dynamic behavior when output is changing
Steady-state behavior when output is hold on 1 or 0 Dynamic behavior when output is changing Electrical behavior of CMOS
The electric model for mos transistor 大Ron大 D G S B G Cg B Cs Ron =Cd Cg: gate capacitor Cd and cs: junction capacitors Ca≈Cs≈3Cg
The electric model for MOS transistor Cg: gate capacitor Cd and Cs: junction capacitors Cd Cs 3Cg
The electric model for basic cmos circuit Rp G D FⅩ F G g Cd Rn Input capacitor: related to gates; Output capacitor: related to junctions; Output resistor: related to the gate area
The electric model for basic CMOS circuit Input capacitor: related to gates; Output capacitor: related to junctions; Output resistor: related to the gate area
The electric model for basic cmos circuit Vcc P net Rp R p input utput N net Rnl Co Co Gnd When state is hold, only r is considered Some voltage must be fallen on r
When state is hold, only R is considered ; Some voltage must be fallen on R ! The electric model for basic CMOS circuit
Steady-state behavior for inverter vout out DD DD Ideal behavior Real behavior The input between Vi and vi should be avoid
Steady-state behavior for inverter Ideal behavior Real behavior The input between VIL and VIH should be avoid !