How to make a better device Good performance faster and less power consumed Low cost more compact and use less area
How to make a better device Low cost : more compact and use less area ! Good performance : faster and less power consumed !
The time delay and area for the simple device CC Vcc 2/14-4 NOR out n12n/1 out NAND(n) Gnd Gnd =10n+2 A=n+2n t,=1ln+1 n+n
The time delay and area for the simple device t d 10n 2 A n 2n 2 = + = + t d = n + A = n + n 2 11 1 2
Fan-in The input numbers of a single gate When fan-in decrease, the device is better The time delay is proportional to the fan-in t4≈10.n The logic area is proportional to the square of fan-in
Fan-in :The input numbers of a single gate When fan-in decrease, the device is better ! The time delay is proportional to the fan-in ! 10 0 t n t d The Logic area is proportional to the square of fan-in !
Use parallel design to limit the fan-in RANDL RAND8 nOPA RANDL tx≈84 ≈42+22+12=76 A≈80 A≈48+10+3=6 If the fan-in is greater than 5, it should be instead by parallel circuit
Use parallel design to limit the fan-in If the fan-in is greater than 5 , it should be instead by parallel circuit ! 80 84 A t d 48 10 3 61 42 22 12 76 + + = + + = A t d
Use parallel design for positive output gate PANDL RAND2 NOP2 AND4 NOP2 oR4 t,≈40+10=50t≈20+20=40 The fan-in should be less than 4 i
Use parallel design for positive output gate 40+10 = 50 t d 20 + 20 = 40 d t The fan-in should be less than 4 !