高级计算机体系结构设计及其在数据中心和云计算的应用Stage 3: Execute DiagramtargetI+d+dneaTV7RoarUMrUXeoedestRegdataID / EXEX/MemPipeline registerPipeline register
高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 3: Execute Diagram regA contents contents ALU result PC + 1 + PC+1 +offset A L M U Decode Memory target ID / EX Pipeline register reg B contents EX/Mem Pipeline register Control signals Control signals regB contents M U U X Decode Memory destReg data
高级计算机体系结构设计及其在数据中心和云计算的应用Stage 4: MemoryPerformdatacacheaccess-ALUresultcontainsaddressforLDorST- Opcode bits control R/W and enable signalsWrite state to the pipeline register (Mem/WB)-ALUresultandLoadeddata- Control signals (from insn) for opcode and destReg
高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 4: Memory • Perform data cache access – ALU result contains address for LD or ST – Opcode bits control R/W and enable signals • Write state to the pipeline register (Mem/WB) – ALU result and Loaded data – Control signals (from insn) for opcode and destReg
高级计算机体系结构设计及其在数据中心和云计算的应用Stage 4: Memory Diagramstarget1OEVCEVin dataaeonrin_addrData CacheR/WenononesedestRegdataEX/MemMem/WBPipeline registerPipeline register
高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 4: Memory Diagram ALU result ALU result PC+1 +offset Loaded in_data Execute Write-back target Mem/WB Pipeline register EX/Mem Pipeline register Control signals reg B contents Loaded Data Cache data en R/W in_addr Control signals Execute Write destReg data
高级计算机体系结构设计及其在数据中心和云计算的应用Stage 5: Write-backWritingresulttoregisterfile(ifrequired)- Write Loaded data to destReg for LD-WriteALU resultto destRegfor arithmeticinsn-Opcodebitscontrolregisterwriteenablesignal
高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 5: Write-back • Writing result to register file (if required) – Write Loaded data to destReg for LD – Write ALU result to destReg for arithmetic insn – Opcode bits control register write enable signal
高级计算机体系结构设计及其在数据中心和云计算的应用Stage 5: Write-back DiagramCEVpaeono7dataUXeesMdestRegUXMem/WBPipeline register
高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 5: Write-back Diagram ALU result Loaded data M Memory Mem/WB Pipeline register Control signals Loaded M U X data destReg M U X Memory