高级计算机体系结构设计及其在数据中心和云计算的应用Stage 1: Fetch. Fetch an instruction from memory every cycle- UsePCtoindexmemory-IncrementPC(assumenobranchesfornow)Write state to the pipeline register (IF/ID)- The next stage will read this pipeline register
高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 1: Fetch • Fetch an instruction from memory every cycle – Use PC to index memory – Increment PC (assume no branches for now) • Write state to the pipeline register (IF/ID) – The next stage will read this pipeline register
高级计算机体系结构设计及其在数据中心和云计算的应用Stage 1: Fetch Diagramtarget.MU十I+OdaPCosInstructionSCacheerIF / IDPipelineregister
高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 1: Fetch Diagram 1 + M U X PC + 1 Decode target Instruction bits IF / ID Pipeline register PC Instruction Cache en en Decode
高级计算机体系结构设计及其在数据中心和云计算的应用Stage 2: DecodeDecodesopcodebits- Set up Control signals forlater stagesReadinputoperandsfromregisterfile-Specified bydecodedinstructionbitsWrite state to the pipeline register (ID/EX)-Opcode- Register contents- PC+1 (even though decode didn't use it)- Control signals (from insn) for opcode and destReg
高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 2: Decode • Decodes opcode bits – Set up Control signals for later stages • Read input operands from register file – Specified by decoded instruction bits • Write state to the pipeline register (ID/EX) – Opcode – Register contents – PC+1 (even though decode didn’t use it) – Control signals (from insn) for opcode and destReg
高级计算机体系结构设计及其在数据中心和云计算的应用Stage 2: Decode DiagramtargetI+I+OdregAearegBeeiRegisterFiledestRegdataSaeesIF / IDID/EXPipelineregisterPipelineregister
高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 2: Decode Diagram regA contents Register File regA regB PC + 1 PC + 1 Fetch Execute destReg target ID / EX Pipeline register regB contents Register File en Instruction bits IF / ID Pipeline register Control signals Fetch Execute destReg data
高级计算机体系结构设计及其在数据中心和云计算的应用Stage 3: Execute.PerformALUoperations- Calculate result of instruction·Control signals select operation·Contentsof regAusedas oneinput: Either regB or constant offset (from insn) used as second input-CalculatePC-relativebranchtargetPC+1+(constantoffset) Write state to the pipeline register (EX/Mem)- ALU result, contents of regB, and PC+1+offset- Control signals (from insn) for opcode and destReg
高级计算机体系结构设计及其在数据中心和云计算的应 用 Stage 3: Execute • Perform ALU operations – Calculate result of instruction • Control signals select operation • Contents of regA used as one input • Either regB or constant offset (from insn) used as second input – Calculate PC-relative branch target • PC+1+(constant offset) • Write state to the pipeline register (EX/Mem) – ALU result, contents of regB, and PC+1+offset – Control signals (from insn) for opcode and destReg