高级计算机体系结构设计及其在数据中心和云计算的应用Lecture 5Core Pipelining
高级计算机体系结构设计及其在数据中心和云计算的应 用 Lecture 5 Core Pipelining
高级计算机体系结构设计及其在数据中心和云计算的应用Before there was pipelining..Single-cycleinsno.(fetch,decodeexec)insn1.(fetch,decode,execMulti-cycleinsno.fetchinsno.decinsn0.execinsn1.fetchinsn1.decinsn1.exectimeSingle-cycle control:hardwired Low CPI (1)- Long clock period (to accommodate slowest instruction)Multi-cycle control:micro-programmed-Shortclockperiod- High CPICan we have both low CPl and short clock period?
高级计算机体系结构设计及其在数据中心和云计算的应 用 Before there was pipelining. • Single-cycle control: hardwired Single-cycle Multi-cycle insn0.(fetch,decode,exec) insn1.(fetch,decode,exec) insn0.fetch insn0.dec insn0.exec insn1.fetch insn1.dec insn1.exec time – Low CPI (1) – Long clock period (to accommodate slowest instruction) • Multi-cycle control: micro-programmed – Short clock period – High CPI • Can we have both low CPI and short clock period?
高级计算机体系结构设计及其在数据中心和云计算的应用PipeliningMulti-cycleinsno.fetchinsno.decinsn0.execinsn1.fetchinsn1.execinsn1.decinsno.fetchinsno.decinsno.execPipelinedinsn1.execinsn1.fetchinsn1.dectimeinsn2.fetchinsn2.decinsn2.execStart with multi-cycle designWhen insnO goes from stage 1 to stage 2... insn1 starts stage 1Each instruction passes through all stages.. but instructions enter and leave at faster rateCan have asmany insns in flight as there are stages
高级计算机体系结构设计及其在数据中心和云计算的应 用 Pipelining • Start with multi-cycle design Multi-cycle insn0.fetch insn0.dec insn0.exec insn1.fetch insn1.dec insn1.exec time Pipelined insn0.fetch insn0.dec insn0.exec insn1.fetch insn1.dec insn1.exec insn2.fetch insn2.dec insn2.exec • When insn0 goes from stage 1 to stage 2 . insn1 starts stage 1 • Each instruction passes through all stages . but instructions enter and leave at faster rate Can have as many insns in flight as there are stages
高级计算机体系结构设计及其在数据中心和云计算的应用PipelineExamples11addresshit?Stage delay = nBandwidth = ~(1/n)Dhit?addressStage delay =n/2Bandwidth = ~(2/naddresshit?Stage delay = n/3一Bandwidth = ~(3/n)Increasesthroughput at the expense of latency
高级计算机体系结构设计及其在数据中心和云计算的应 用 Pipeline Examples address hit? = = = = address = hit? = Increases throughput at the expense of latency = = = address hit? = = = =
高级计算机体系结构设计及其在数据中心和云计算的应用Processor PipelineReviewDecodeFetchExecuteMemory(Write-back)RegALUI-cacheD-cacheFile
高级计算机体系结构设计及其在数据中心和云计算的应 用 Processor Pipeline Review +4 Fetch Decode Memory (Write-back) Execute I-cache Reg File PC +4 ALU D-cache