Pipelined Control SignalsD/EXEX/MEMMEMWEF/DAddDAdresultALUSrCReadregister1AddressonReaddata 1Readregister2InstructfionALURegistersReadALUmemoryReadWriteAddressdata 2resultdataregisterDatamemoryWritedataWritedataInstruction 1632[15-0]SignALUMemReadextendcontrolInstructior[20-16]ALUOpMuxInstruction[15-11]RegDstComputerArchitecture26
Computer Architecture Pipelined Control Signals 26 PC Instruction memory Instruction Add Instruction [20– 16] MemtoReg ALUOp Branch RegDst ALUSrc 4 16 32 Instruction [15– 0] 0 0 M u x 0 1 Add Add result Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Sign extend M u x 1 ALU result Zero Write data Read data M u x 1 ALU control Shift left 2 RegWrite MemRead Control ALU Instruction [15– 11] 6 EX M WB M WB WB IF/ID PCSrc ID/EX EX/MEM MEM/WB M u x 0 1 Mem Write Address Data memory Address
AnldealPipeline Goal: Increase throughput with little increase in cost(hardware cost, in case of instruction processing):Repetition of identical operations. The same operation is repeated on a large number ofdifferent inputsRepetition of independentoperations-Nodependenciesbetweenrepeatedoperations.Uniformly partitionable suboperations- Processing an be evenly divided into uniform-latencysuboperations (that do not share resources) Fitting examples: automobile assembly line, doinglaundry- What about the instruction processing "cycle"?ComputerArchitecture27
Computer Architecture An Ideal Pipeline • Goal: Increase throughput with little increase in cost (hardware cost, in case of instruction processing) • Repetition of identical operations – The same operation is repeated on a large number of different inputs • Repetition of independent operations – No dependencies between repeated operations • Uniformly partitionable suboperations – Processing an be evenly divided into uniform-latency suboperations (that do not share resources) • Fitting examples: automobile assembly line, doing laundry – What about the instruction processing “cycle”? 27
InstructionPipeline:NotAnIdealPipelineIdentical operations ... NOT!= different instructions do not need all stages-Forcingdifferent instructionstogothroughthesamemulti-function pipeexternal fragmentation (somepipe stages idleforsome instructions)Uniform suboperations ... NOT!difficulttobalancethe differentpipeline stages-Notallpipelinestagesdothesameamountofworkinternal fragmentation (some pipe stages aretoo-fast but takethe sameclock cycle time)Independent operations ... NOT!instructionsarenotindependentofeachother-Needtodetectand resolveinter-instructiondependenciesto ensurethepipelineoperates correctly> Pipeline is not always moving (it stalls)ComputerArchitecture28
Computer Architecture InstrucBon Pipeline: Not An Ideal Pipeline • IdenBcal operaBons . NOT! ⇒ different instrucBons do not need all stages - Forcing different instrucBons to go through the same mulB-funcBon pipe à external fragmentaBon (some pipe stages idle for some instrucBons) • Uniform suboperaBons . NOT! ⇒ difficult to balance the different pipeline stages - Not all pipeline stages do the same amount of work à internal fragmentaBon (some pipe stages are too-fast but take the same clock cycle Bme) • Independent operaBons . NOT! ⇒ instrucBons are not independent of each other - Need to detect and resolve inter-instrucBon dependencies to ensure the pipeline operates correctly à Pipeline is not always moving (it stalls) 28
IssuesinPipelineDesign.Balancing work in pipeline stages- How many stages and what is done in each stage Keeping the pipeline correct, moving, and full in thepresence of events that disrupt pipeline flow- Handling dependences: Data. Control-Handling resource contention Handling long-latency (multi-cycle) operationsHandling exceptions, interrupts: Advanced: Improving pipeline throughput-Minimizing stallsComputerArchitecture29
Computer Architecture Issues in Pipeline Design • Balancing work in pipeline stages – How many stages and what is done in each stage • Keeping the pipeline correct, moving, and full in the presence of events that disrupt pipeline flow – Handling dependences • Data • Control – Handling resource contention – Handling long-latency (multi-cycle) operations • Handling exceptions, interrupts • Advanced: Improving pipeline throughput – Minimizing stalls 29
Causes of Pipeline Stalls· Resource contention: Dependences (between instructions)- Data- Control: Long-latency (multi-cycle) operationsComputerArchitecture30
Computer Architecture Causes of Pipeline Stalls • Resource contention • Dependences (between instructions) – Data – Control • Long-latency (multi-cycle) operations 30