PipelinedOperationExamplesub$11,$2,$3WritebackEMWBister1ddressReaddata1ReatnstructiorReoistersALRecmemonWriteRedata2egistedatDataWritememoryatWrite32Clock621ComputerArchitecture
Computer Architecture Pipelined OperaBon Example 21 Instruction memory Address 4 32 0 Add Add result Shift left 2 Instruction IF/ID EX/MEM MEM/WB M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data 1 ALU result M u x ALU Zero ID/EX Instruction decode lw $10, 20($1) Instruction fetch sub $11, $2, $3 Instruction memory Address 4 32 0 Add Add result Shift left 2 Instruction IF/ID EX/MEM MEM/WB M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data 1 ALU result M u x ALU Zero ID/EX Instruction fetch lw $10, 20($1) Address Data memory Address Data memory Clock 1 Clock 2 Instruction memory Address 4 32 0 Add Add result Shift left 2 Instruction IF/ID EX/MEM MEM/WB M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data 1 ALU result M u x ALU Zero ID/EX Instruction decode lw $10, 20($1) Instruction fetch sub $11, $2, $3 Instruction memory Address 4 32 0 Add Add result Shift left 2 Instruction IF/ID EX/MEM MEM/WB M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data 1 ALU result M u x ALU Zero ID/EX Instruction fetch lw $10, 20($1) Address Data memory Address Data memory Clock 1 Clock 2 Instruction memory Address 4 0 Add Add result Shift left 2 Instruction IF/ID EX/MEM MEM/WB M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 32 Sign extend Write register Write data Memory lw $10, 20($1) Read data 1 ALU result M u x ALU Zero ID/EX Execution sub $11, $2, $3 Instruction memory Address 4 0 Add Add result Shift left 2 Instruction IF/ID EX/MEM MEM/WB M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 Write register Write data Read data 1 ALU result M u x ALU Zero ID/EX Execution lw $10, 20($1) Instruction decode sub $11, $2, $3 16 32 Sign extend Address Data memory Data memory Address Clock 3 Clock 4 Instruction memory Address 4 0 Add Add result Shift left 2 Instruction IF/ID EX/MEM MEM/WB M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 32 Sign extend Write register Write data Memory lw $10, 20($1) Read data 1 ALU result M u x ALU Zero ID/EX Execution sub $11, $2, $3 Instruction memory Address 4 0 Add Add result Shift left 2 Instruction IF/ID EX/MEM MEM/WB M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 Write register Write data Read data 1 ALU result M u x ALU Zero ID/EX Execution lw $10, 20($1) Instruction decode sub $11, $2, $3 16 32 Sign extend Address Data memory Data memory Address Clock 3 Clock 4 Instruction memory Address 4 32 0 Add Add result 1 ALU result Zero Shift left 2 Instruction IF/ID ID/EX EX/MEM MEM/WB Write back M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend M u x ALU Read data Write register Write data lw $10, 20($1) Instruction memory Address 4 32 0 Add Add result 1 ALU result Zero Shift left 2 Instruction IF/ID ID/EX EX/MEM MEM/WB Write back M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend M u x ALU Read data Write register Write data sub $11, $2, $3 Memory sub $11, $2, $3 Address Data memory Address Data memory Clock 6 Clock 5 Instruction memory Address 4 32 0 Add Add result 1 ALU result Zero Shift left 2 Instruction IF/ID ID/EX EX/MEM MEM/WB Write back M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend M u x ALU Read data Write register Write data lw $10, 20($1) Instruction memory Address 4 32 0 Add Add result 1 ALU result Zero Shift left 2 Instruction IF/ID ID/EX EX/MEM MEM/WB Write back M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend M u x ALU Read data Write register Write data sub $11, $2, $3 Memory sub $11, $2, $3 Address Data memory Address Data memory Clock 6 Clock 5
Illustrating Pipeline Operation:Operation ViewKAtoXSt1t3t2IFIDEXMEMWBInstoLIFIDInstiEXMEMWBIFEXIDWBInst2MEMIFIDEXMEMWBInst3IFIDEXMEMInst4IFIDEXIFIDMMIFComputerArchitecture22
Computer Architecture IllustraBng Pipeline OperaBon: OperaBon View 22 MEM EX ID Inst IF 4 WB IF MEM IF MEM EX t0 t1 t2 t3 t4 t5 ID IF ID EX IF ID Inst0 ID Inst IF 1 EX ID Inst IF 2 MEM EX ID Inst IF 3 WB MEM WB EX WB
IllustratingPipelineOperation:ResourceViewtit2t3t4tstttgtgtot1o15IF161417Ig1112131g110IDIs1417lg121316I80EX16213141531?10MEM1s11121314161710WB1415161112131oComputerArchitecture23
Computer Architecture IllustraBng Pipeline OperaBon: Resource View 23 I0 I0 I1 I0 I1 I2 I0 I1 I2 I3 I0 I1 I2 I3 I4 I1 I2 I3 I4 I5 I2 I3 I4 I5 I6 I3 I4 I5 I6 I7 I4 I5 I6 I7 I8 I5 I6 I7 I8 I9 I6 I7 I8 I9 I10 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 IF ID EX MEM WB
Control Pointsin a PipelineIF/IDEXIMEMMEMWBD/EXReoriReateisterAddressReaddataReadMemtoReInstructionRegistersReaReadwitedata 2AddressregistedatDatawaitememoryWritedata[15-0MemReadneir[20-16]Instruction[1511]Identicalset of control points asthesingle-cycledatapath!!ComputerArchitecture24
Computer Architecture Control Points in a Pipeline 24 PC Instruction memory Address Instruction Instruction [20– 16] MemtoReg ALUOp Branch RegDst ALUSrc 4 16 32 Instruction [15– 0] 0 0 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Sign extend M u x 1 Write data Read data M u x 1 ALU control RegWrite MemRead Instruction [15– 11] 6 IF/ID ID/EX EX/MEM MEM/WB MemWrite Address Data memory PCSrc Zero Add Add result Shift left 2 ALU result ALU Zero Add 0 1 M u x 0 1 M u x IdenBcal set of control points as the single-cycle datapath!!
Control SignalsinaPipelineForagiven instructionsamecontrolsignalsassingle-cycle,but-controlsignalsrequiredatdifferentcycles,dependingonstagedecodeonceusingthesamelogicassingle-cycleandbuffercontrol signalsuntilconsumedWRInstructionControlEX/MEMMEM/WBIF/IDID/EX→or carryrelevant"instructionword/field”down thepipelineand decodelocallywithineachstage(still samelogic)Whichoneisbetter?ComputerArchitecture25
Computer Architecture Control Signals in a Pipeline • For a given instrucBon – same control signals as single-cycle, but – control signals required at different cycles, depending on stage ⇒decode once using the same logic as single-cycle and buffer control signals unBl consumed ⇒or carry relevant “instrucBon word/field” down the pipeline and decode locally within each stage (sBll same logic) Which one is be*er? 25 Control EX M WB M WB WB IF/ID ID/EX EX/MEM MEM/WB Instruction