STM32L431xx Functional overview Legend:Y-Yes(Enable).=Opional(Disable by default.Can be enabled by software).-Not available. 2.The Flash can be configured in power-down mode.By default.it is not in power-down mode. The SRAM clock can be gated on or of ed when the bit RRS is set in PWR_CR3 register. 品器品 6. 2C addre in Stop mode,and generateswakeup interrupt in case of address match Voltage scaling Rang e 1 only. Os can be 11.a eouredir rion is lost when 3.9.5 Reset mode deactivated when the reset source is internal. 3.9.6 VBAT operation device VRAT do en no ex vith LSE and the backup registers.Three anti- VBAT operation is automatically activated when Vop is not present. Note: suppliedfrom VBAT,extemal inteuptsand RTCala/events 3.10 Interconnect matrix U r s.the ctions can operate in Run.Sleep.low-power run le 7 DS11453 Rev 3 31208
DS11453 Rev 3 31/208 STM32L431xx Functional overview 54 3.9.5 Reset mode In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.9.6 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup registers. Three antitamper detection pins are available in VBAT mode. VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 3.10 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes. 1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. 2. The Flash can be configured in power-down mode. By default, it is not in power-down mode. 3. The SRAM clock can be gated on or off. 4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. 5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 8. Voltage scaling Range 1 only. 9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode
Functional overview STM32L431xx Table 6.STM32L431xx peripherals interconnect matrix Interconnect source Interconnect action TIMX Timers synchronization or chaining ADCx Conversion triggers TIMx DAC1 DMA Memory to memory transfer trigger YYYY-- COMPX Comparator output blanking TIM15/TIM16 IRTIM Infrared interface output generation YYYY - TIM1 COMPX TIM2 YYYY LPTIMERx ADCx Timer triggered by analog watchdog YYYY TIM16 Timer input channel from RTC events RTC LPTIMERx riggered by RTC alarms or tampers All clocks sources (intemal TIM2 and extemal) T1M15.16 YYYY CSS RA(hard faul) TIM1 Timer break YYYY COMPx PVD TIMX Extemal trigger YYYY-- LPTIMERx Extemal trigger YYYYY d GPIO ADCX DAC1 Conversion extemal trigge YYYY 32/208 DS11453 Rev 3 7
Functional overview STM32L431xx 32/208 DS11453 Rev 3 Table 6. STM32L431xx peripherals interconnect matrix Interconnect source Interconnect destination Interconnect action Run Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 TIMx TIMx Timers synchronization or chaining Y Y Y Y - - ADCx DAC1 Conversion triggers Y Y Y Y - - DMA Memory to memory transfer trigger Y Y Y Y - - COMPx Comparator output blanking Y Y Y Y - - TIM15/TIM16 IRTIM Infrared interface output generation Y Y Y Y - - COMPx TIM1 TIM2 Timer input channel, trigger, break from analog signals comparison YYYY - - LPTIMERx Low-power timer triggered by analog signals comparison YYYYY Y (1) ADCx TIM1 Timer triggered by analog watchdog Y Y Y Y - - RTC TIM16 Timer input channel from RTC events Y Y Y Y - - LPTIMERx Low-power timer triggered by RTC alarms or tampers YYYYY Y (1) All clocks sources (internal and external) TIM2 TIM15, 16 Clock source used as input channel for RC measurement and trimming YYYY - - CSS CPU (hard fault) RAM (parity error) Flash memory (ECC error) COMPx PVD TIM1 TIM15,16 Timer break Y Y Y Y - - GPIO TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y Y (1) ADCx DAC1 Conversion external trigger Y Y Y Y - - 1. LPTIM1 only
STM32L431xx Functional overview 3.11 Clocks and startup roller (see Fig diffe ensures clock robustness.It features: Clock prescaler:to get the best trade-off between speed and current consumption frequency to the CPU and peripherals can be adjusted by a programmable through a configuration register. rces can be changed safely on the fly in run mode Clock management:to reduce power consumption,the clock controller can stop the clock to the core.individual peripherals or memory. System clock source:four different clock sources can be used to drive the master clock SYSCLK scllator(HS16).trimmable by software,that can Mult peed internal rc oscillator (MSD)trimmable t ahle to frequency can b ned by PLLwhich can be fed by HSE.HS16 or MSI with a maximum frequency n(HS148):internal RC48 MHz clock source can be egayeckourcertwouhaowpoercoeksourcesthatcanbeusendne 32768kH - speed internal RC(LSI).also used to drive the independent watchdog Peripheral clock sources:Several peripherals(SDMMC.RNG.SAI,USARTs,12Cs SWPMI)have their ov ent clock wha e syste generate independent clocks for the ADC.the SDMMC/RNG and the SAl. lity,car Startup clock:after reset,the microcontroller restarts by default with an internal 4 MHz S).The prescaler ratio andcanged by the application program as soon as the co ):be nb re 7 DS11453 Rev 3 33/208
DS11453 Rev 3 33/208 STM32L431xx Functional overview 54 3.11 Clocks and startup The clock controller (see Figure 4) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: four different clock sources can be used to drive the master clock SYSCLK: – 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL. – System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 80 MHz. • RC48 with clock recovery system (HSI48): internal RC48 MHz clock source can be used to drive the SDMMC or the RNG peripherals. This clock can be output on the MCO. • Auxiliary clock source: two ultralow-power clock sources that can be used to drive the real-time clock: – 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock. – 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock accuracy is ±5% accuracy. • Peripheral clock sources: Several peripherals (SDMMC, RNG, SAI, USARTs, I2Cs, LPTimers, ADC, SWPMI) have their own independent clock whatever the system clock. Two PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the SDMMC/RNG and the SAI. • Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software
Functional overview STM32L431xx inter upt is generated if enabled.LSE failure can aso be detected and generated an interrupt. .Clock-out capability MCO:microcontroller clock output:it outputs one of the intemal clocks for extemofrequency clocks (SI.LSE)are avallable uput:it o LSCO is not available in VBAT mode. ed APB(AP f the AHB 34/208 DS11453 Rev 3 7
Functional overview STM32L431xx 34/208 DS11453 Rev 3 interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state. – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes down to Standby mode. LSE can also be output on LSCO in Shutdown mode. LSCO is not available in VBAT mode. Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz
STM32L431xx Functional overview Figure 4.Clock tree to IWDG OSC32_OUT 11-16 o AHB bus,core,mo /M PCLK2 CRS SA1_EXTCLK to SAl1 M5A020EV 7 DS11453 Rev 3 35/208
DS11453 Rev 3 35/208 STM32L431xx Functional overview 54 Figure 4. Clock tree MSv39206V3 SYSCLK MCO LSCO 48 MHz clock to RNG, SDMMC to ADC to IWDG to RTC to PWR HCLK to AHB bus, core, memory and DMA FCLK Cortex free running clock to Cortex system timer to APB1 peripherals to APB2 peripherals PCLK1 PCLK2 to SAI1 LSE HSI16 SYSCLK to USARTx x=2..3 to LPUART1 to I2Cx x=1,2,3 to LPTIMx x=1,2 SAI1_EXTCLK to SWPMI to TIMx x=2,6,7 OSC32_OUT OSC32_IN MSI HSI16 HSE HSI16 LSI LSE HSE SYSCLK HSE MSI HSI16 MSI SYSCLK LSE OSC 32.768 kHz /32 AHB PRESC / 1,2,..512 / 8 APB1 PRESC / 1,2,4,8,16 x1 or x2 HSI16 SYSCLK LSI LSE HSI16 HSI16 APB2 PRESC / 1,2,4,8,16 to TIMx x=1,15,16 x1 or x2 to USART1 LSE HSI16 SYSCLK / M MSI RC 100 kHz – 48 MHz HSI RC 16 MHz HSE OSC 4-48 MHz Clock detector OSC_OUT OSC_IN / 1→16 LSI RC 32 kHz Clock source control PLLSAI1CLK PLL48M1CLK PLLCLK PLLSAI2CLK PLL48M2CLK PLLADC1CLK HSI16 HSI16 HSI RC 48 MHz HSI48 CRS PLL PLLSAI1 VCO FVCO / P / R / Q / P / Q / R VCO FVCO PLLCLK MSI