高职嵌入式教材配套电子资源（技术资料）STM32L4xx参考手册（RM0394 Reference manual）advanced Arm-based 32-bit MCUs

RM0394 e.augmented Reference manual STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx advanced Arm-based 32-bit MCUs Introduction ual targets application devel vides complete information peripherals. The STM32L41xxx/42xXx/43xxx/44xxx/45xxx/46xxx is a family of microcontrollers with different memory sizes,packages and peripherals. mechanical and electrical device characteristics please refer to the Related documents Cortex-M4 Technical Reference Manual,available from:http://infocenter.arm.com STM32L412XX STM321422XX STM321431 STM321432XX STM321433xX STM32L442xx STM32L443X,STM32L451xx STM32L452xx STM32L462xx datasheets STM32F3.STM32F4.STM32L4 and STM32L4+Series Cortex-M4(PM0214) October 2018 RM0394 Rev4 1V160 www.st.com

October 2018 RM0394 Rev 4 1/1600 1 RM0394 Reference manual STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx advanced Arm®-based 32-bit MCUs Introduction This reference manual targets application developers. It provides complete information on how to use the STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx microcontroller memory and peripherals. The STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets. For information on the Arm® Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual. Related documents • Cortex®-M4 Technical Reference Manual, available from: http://infocenter.arm.com • STM32L412xx, STM32L422xx, STM32L431xx, STM32L432xx, STM32L433xx, STM32L442xx, STM32L443xx, STM32L451xx, STM32L452xx, STM32L462xx datasheets • STM32F3, STM32F4, STM32L4 and STM32L4+ Series Cortex®-M4 (PM0214) www.st.com

Contents RM0394 Contents Documentation conventions.................................60 1.1 General information..........................................60 1.2 List of abbreviations for registers...............................60 1.3 Glossary...............61 1.4 Availability of peripherals 61 1.5 Product specific features .,.61 System and memory overview 000gggg。g0g000000080000800800g 63 2.1 System architecture 63 2.1.1 80:hbus................................................64 212 S1:D-bus」 2.1.3 S2:S-bus 0……。。4。。。。……。…“。……。…。……。… 65 2.1.4 S3,S4:DMA-bus.................................... 2.15 BusMatrix 2.2 Memory organization........................................ 66 2.21 Introduction 2.2.2 Memory map and register boundary addresses............. 2.3 Bit banding…70 2.4 Embedded SRAM.................71 2.4.1 SRAM2 parity check 2.4.2 SRAM2 Write protection....................................72 243 SRAM2 Read protection ..73 2.4.4 SRAM2Erase.................................... 73 2.5 Flash memory overview 7 2.6 Bootconfiguration..........................................74 3 Embedded Flash memory (FLASH)........................... .77 3.1 Introduction.. ..77 32 FLASH main features........................................ 3.3 FLASH functional description .77 3.3.1 Flash memory organization 77 3.3.2 Error code correction (ECC) ....78 3.3.3 Read access latency 2/1600 RM0394Rev4 7

Contents RM0394 2/1600 RM0394 Rev 4 Contents 1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.4 Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.5 Product specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2 System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.1.1 S0: I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.1.2 S1: D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.1.3 S2: S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.1.4 S3, S4: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.1.5 BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 67 2.3 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.1 SRAM2 parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.2 SRAM2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.4.3 SRAM2 Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.4.4 SRAM2 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.5 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.6 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3 Embedded Flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.2 FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3 FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3.1 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3.2 Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.3.3 Read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

RM0394 Contents 3.3.4 Adaptive real-time memory accelerator (ART AcceleratorTM) 80 3.35 Flash program and erase operations .82 3.3.6 Flash main memory erase sequences ..........................83 3.3.7 Flash main memory programming sequences 3.4 FLASH option bytes 88 34.1 Option bytes description 3.4.2 Option bytes programming............................. .92 35 FLASH memory protection 3.5.1 Read protection(RDP) 94 3.52 Proprietary code readout protection(PCROP) 35.3 Write protection(WRP) 。，。 3.6 FLASH interrupts 3.7 FLASHregisters...........................................100 3.7.1 Flash access control register(FLASH_ACR) 100 3.7.2 Flash Power-down key register(FLASH_PDKEYR) 3.73 Flash key register(FLASH KEYR). 3.74 Flash option key register(FLASH_OPTKEYR 102 3.7.5 Flash status register (FLASH_SR)....................... 102 3.7.6 Flash control register(FLASH_CR) 104 3.77 Flash ECC register(FLASH_ECCR) 106 3.7.8 Flash option register (FLASH OPTR) 107 3.7.9 Flash PCROP Start address register(FLASH_PCROP1SR) 109 3.7.10 Flash PCROP End address register(FLASH PCROP1ER) .109 3711 Flash WRP area A address register(FLASH WRP1AR) ,110 37.12 Flash WRP area B address register (FLASH_WRP1BR) 3.7.13 .112 Firewall (FW) 114 4.1 Introduction 114 4.2 Firewall main features 。。。。，。。 .114 4.3 Firewall functional description .115 4.3.1 Firewall AMBA bus snoop ............................ ,115 4.32 Functional requirements 115 43.3 Firewall segments 116 4.3.4 Segment accesses and properties...........................117 4.3.5 Firewall initialization ..118 RM0394 Rev4 3/1600

RM0394 Rev 4 3/1600 RM0394 Contents 43 3.3.4 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 80 3.3.5 Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.3.6 Flash main memory erase sequences . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.3.7 Flash main memory programming sequences . . . . . . . . . . . . . . . . . . . . 84 3.4 FLASH option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.4.1 Option bytes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.4.2 Option bytes programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.5 FLASH memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.5.1 Read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.5.2 Proprietary code readout protection (PCROP) . . . . . . . . . . . . . . . . . . . 97 3.5.3 Write protection (WRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.6 FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.7 FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.7.1 Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . 100 3.7.2 Flash Power-down key register (FLASH_PDKEYR) . . . . . . . . . . . . . . 101 3.7.3 Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.7.4 Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 102 3.7.5 Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.7.6 Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.7.7 Flash ECC register (FLASH_ECCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.7.8 Flash option register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.7.9 Flash PCROP Start address register (FLASH_PCROP1SR) . . . . . . . 109 3.7.10 Flash PCROP End address register (FLASH_PCROP1ER) . . . . . . . . 109 3.7.11 Flash WRP area A address register (FLASH_WRP1AR) . . . . . . . . . . 110 3.7.12 Flash WRP area B address register (FLASH_WRP1BR) . . . . . . . . . . 110 3.7.13 FLASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4 Firewall (FW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 4.2 Firewall main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 4.3 Firewall functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 4.3.1 Firewall AMBA bus snoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.3.2 Functional requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.3.3 Firewall segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.3.4 Segment accesses and properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.3.5 Firewall initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Contents RM0394 4.3.6 Firewall states 119 4.4 Firewall registers........ 121 441 Code segment start address(FW_CSSA) 2 4.42 Code segment length(FW CSL)..... 4.4.3 Non-volatile data segment start address(FW_NVDSSA) 1 444 Non-volatile data segment length (FW_NVDSL) 122 4.4.5 Volatile data segment start address(FW_VDSSA) .123 4.4.6 Volatile data segment length(FW_VDSL) ,123 4.47 Configuration register (FW CR)............................ 124 4.4.8 Firewall register map.......,......................... 125 Power control(PWR) 126 5.1 Power supplies 126 5.1.1 Independent analog peripherals supply 128 5.1.2 Independent USB transceivers supply 129 513 ndependent LCD supply 129 5.1.4 Battery backup domai ,130 5.15 Voltage reaulator .131 5.1.6 VDD12 domain 132 5.1.7 Dynamic voltage scaling management 133 5.2 Power supply supervisor 135 5.2.1 66mePoRoertaneaPoR1romoae 5.2.2 Programmable voltage detector (PVD)..... 135 523 Peripheral Voltage Monitoring(PVM) 136 5.3 Low-power modes 137 531 Run mode 5.3.2 Low-power run mode (LP run)............................... 4 5.3.3 Low power modes 45 53.4 Sleep mode 14 5.3.5 Low-power sleep mode (LP sleep) 5.3.6 Stop 0 mode 148 5.3.7 Stop1mode........................................ 5.3.8 Stop 2 mode. .151 5.3.9 Standby mode 3 5.3.10 Shutdown mode. 156 5.3.11 Auto-wakeup from low-power mode .157 4/1600 RM0394 Rev 4 7

Contents RM0394 4/1600 RM0394 Rev 4 4.3.6 Firewall states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.4 Firewall registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.4.1 Code segment start address (FW_CSSA) . . . . . . . . . . . . . . . . . . . . . . 121 4.4.2 Code segment length (FW_CSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.4.3 Non-volatile data segment start address (FW_NVDSSA) . . . . . . . . . . 122 4.4.4 Non-volatile data segment length (FW_NVDSL) . . . . . . . . . . . . . . . . . 122 4.4.5 Volatile data segment start address (FW_VDSSA) . . . . . . . . . . . . . . . 123 4.4.6 Volatile data segment length (FW_VDSL) . . . . . . . . . . . . . . . . . . . . . . 123 4.4.7 Configuration register (FW_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.4.8 Firewall register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.1.1 Independent analog peripherals supply . . . . . . . . . . . . . . . . . . . . . . . . 128 5.1.2 Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.1.3 Independent LCD supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.1.4 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.1.5 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.1.6 VDD12 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.1.7 Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . 133 5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 135 5.2.3 Peripheral Voltage Monitoring (PVM) . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.3.1 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.3.2 Low-power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 5.3.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.3.4 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.3.5 Low-power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.3.6 Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.3.7 Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.3.8 Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.3.9 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 5.3.10 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 5.3.11 Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 157

RM0394 Contents 5.4 PWR registers 158 5.4.1 Power control register 1 (PWR CR1) .158 5.4.2 Power control register 2(PWR CR2) 159 5.4.3 Power control register 3(PWR_CR3) 160 5.4.4 Power control reaister 4(PWR CR4) 161 5.4.5 Power status register 1(PWR_SR1) 16x 5.46 Power status register 2(PWR_SR2) 164 5.47 Power status clear register(PWR SCR) 1 54.8 Power Port A pull-up control register(PWR_PUCRA) 166 5.4.9 Power Port A pull-down control register(PWR PDCRA). 166 5.4.10 Power Port B pull-up control register(PWR PUCRB) 167 5.4.11 Power Port B pull-down control register(PWR_PDCRB) 167 5.4.12 Power Port C pull-up control register (PWR PUCRC) .168 5.4.13 Power Port C pull-down control register(PWR_PDCRC) 16g 5414 Power Port D pull-up control register(PWR_PUCRD) 169 5.415 Power Port D pull-down control register(PWR PDCRD) 169 5.416 Power Port E pull-up control register(PWR_PUCRE) 0 5.4.17 Power Port E pull-down control register(PWR PDCRE) ,170 5.4.18 Power Port H pull-up control register(PWR_PUCRH) 171 5.419 Power Port H pull-down control register(PWR_PDCRH) 5.4.20 PWR register map and reset value table .173 Reset and clock control(RCC) 175 6.1 Reset 175 611 Power reset 15 6.1.2 175 6.1.3 Backup domain reset 176 6.2 Clocks...................................................TT 6.21 HSE clock 181 622 HSI16 clock 6.23 MSI clock 183 624 HS148 clock 183 6.2.5 pLL............................................... ,184 6.2.6 LSE clock 185 6.2.7 LSI clock 185 6.2.8 System clock (SYSCLK)selection..................... .185 629 Clock source frequency versus voltage scaling ,186 RM0394 Rev 4 5/1600

RM0394 Rev 4 5/1600 RM0394 Contents 43 5.4 PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.4.1 Power control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.4.2 Power control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.4.3 Power control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.4.4 Power control register 4 (PWR_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.4.5 Power status register 1 (PWR_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.4.6 Power status register 2 (PWR_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.4.7 Power status clear register (PWR_SCR) . . . . . . . . . . . . . . . . . . . . . . . 165 5.4.8 Power Port A pull-up control register (PWR_PUCRA) . . . . . . . . . . . . . 166 5.4.9 Power Port A pull-down control register (PWR_PDCRA) . . . . . . . . . . 166 5.4.10 Power Port B pull-up control register (PWR_PUCRB) . . . . . . . . . . . . . 167 5.4.11 Power Port B pull-down control register (PWR_PDCRB) . . . . . . . . . . 167 5.4.12 Power Port C pull-up control register (PWR_PUCRC) . . . . . . . . . . . . 168 5.4.13 Power Port C pull-down control register (PWR_PDCRC) . . . . . . . . . . 168 5.4.14 Power Port D pull-up control register (PWR_PUCRD) . . . . . . . . . . . . 169 5.4.15 Power Port D pull-down control register (PWR_PDCRD) . . . . . . . . . . 169 5.4.16 Power Port E pull-up control register (PWR_PUCRE) . . . . . . . . . . . . . 170 5.4.17 Power Port E pull-down control register (PWR_PDCRE) . . . . . . . . . . 170 5.4.18 Power Port H pull-up control register (PWR_PUCRH) . . . . . . . . . . . . 171 5.4.19 Power Port H pull-down control register (PWR_PDCRH) . . . . . . . . . . 171 5.4.20 PWR register map and reset value table . . . . . . . . . . . . . . . . . . . . . . . 173 6 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1.1 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6.2.2 HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 6.2.3 MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 6.2.4 HSI48 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 6.2.5 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.2.6 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.2.7 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.2.8 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.2.9 Clock source frequency versus voltage scaling . . . . . . . . . . . . . . . . . . 186