28/208 Table 4.STM32L431xx modes overview (continued) Mode Regulator(1) CPU Flash SRAM Clocks DMA Peripherals(2 Wakeup source Consumption(3) Wakeup time LPR SRAM BOR,RTC.IWDG 0.20μAwo RTC 2ON 0.46μAw/RTC LSE All other peripherals are Reset pin Standby Power off ed Off Powe LSI powered off. 5Os(KUPx)间 12.2s Functional overview OFF ed BOR,RTC,IWDG 0.03μA wto RT0 1/O configuration can be 0.29μAW/RTC floating.pull-up or pull-down All other peripherals are Reset pin Shutdown OFF Power LSE powered off. 0.01μA wo RTC ed Off 5 LOs (WKUPx)(9) 0.20μAw/RTC 2624s Off I/O configuration can be RTC oarpul- LPR mea s Main reg and Ow-pow ON 23 All peripherals can be active or clock gated to Voo-1.8V.25C. Consumptions values provided running from SRAM,Flash memory Off,80 MHz in Range 1,26 MHz in Range 2.2 MHz in The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. The SRAM1 and SRAM2 clocks can be gated on or off independently. 6. U(S)ART and LPUART reception is functional in Stop mode,and gene ates a wakeup interrupt on Start,address matc or received frame event. 2 12C address detection is functional in Stop mode,and generates a wakeup intemupt in case of address match. & wakeup by resume from suspe d 9.The l/Os with wakeup from Standby/Shutdown apabality are:PAO,PC13,PE6.PA2,PC5. 10.LOs can be configured with intemal pull-up.pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. 白 STM32L431XX
26/208 DS11453 Rev 3 Functional overview STM32L431xx Standby LPR Power ed Off Off SRAM 2 ON LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pull-down Reset pin 5 I/Os (WKUPx)(9) BOR, RTC, IWDG 0.20 µA w/o RTC 0.46 µA w/ RTC 12.2 µs OFF Power edOff 0.03 µA w/o RTC 0.29 µA w/ RTC Shutdown OFF Power ed Off Off Power edOff LSE RTC *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pull- down(10) Reset pin 5 I/Os (WKUPx)(9) RTC 0.01 µA w/o RTC 0.20 µA w/ RTC 262 µs 1. LPR means Main regulator is OFF and Low-power regulator is ON. 2. All peripherals can be active or clock gated to save power consumption. 3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in LPRun/LPSleep. 4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. 5. The SRAM1 and SRAM2 clocks can be gated on or off independently. 6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 8. SWPMI1 wakeup by resume from suspend. 9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. Table 4. STM32L431xx modes overview (continued) Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
STM32L431xx Functional overview eiosgeaoneoheielprea8eieaeleorapowerResLtsupohe By default,the micro ntroller is in Run Sleep mode In Sleep mode.only the CPU is stopped.All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Low-power run mode This mode is achieved with R supplied by the low-power reguator to minimize the om h indepe be clocked by HS116. Low-power sleep mode This mode is entered from the low power run mode Stop 0,Stop 1 and Stop 2 modes running The RTC can remain active(Stop mode with RTC.Stop mode without RTC). 8adochahcoaiRanatyenenebeeHsi6Rcdingsepmao age mode ber of Stop 2. D0 as remnsON.very fast wakeup time put with much higher consumption. Standby mode The Standby mode is used to achieve the lowest power consumption with BOR.The oso that the e PLL,the The RTC can Sta dby m de with RTC St dby mode without RTC) The browo reset(BOR)always remains active in St oy mo intemap-uintempu can be selected by software:I/O with SPAM1 and ters in the Backup domain and Standby circuitry.Optionally.SRAM2 can be retained in Standby mode.supplied by the low-power Regulator(Standby with SRAM2 retention when an ext emal reset s(a periodic wakeup.timestamp.tamper)or failure is detected on). The system clock after wakeup is MSI up to 8 MHz. 7 DS11453 Rev 3 271208
DS11453 Rev 3 27/208 STM32L431xx Functional overview 54 By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. • Low-power sleep mode This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode. • Stop 0, Stop 1 and Stop 2 modes Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition. Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption. The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration. • Standby mode The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The brown-out reset (BOR) always remains active in Standby mode. The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating. After entering Standby mode, SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention mode). The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE). The system clock after wakeup is MSI up to 8 MHz
Functional overview STM32L431xx 。 Shutdown mode o achieve the lov the MSI,the LSI and the HSEoscillatorare also switched off. The RTC can remain active (Shutdown mode with RTC.Shutdown mode without RTC) The BOR is not available in Shutdown mode.No power voltage monitoring is possible in this mode,therefore the switch to Backup domain is not supported RAM1,SRAM2 and register contents are ost except for registers in the Backup e r (al .me8 m.tam3p8月 The system clock after wakeup is MSI at 4 MHz. 28/208 DS11453 Rev 3 7
Functional overview STM32L431xx 28/208 DS11453 Rev 3 • Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported. SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain. The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper). The system clock after wakeup is MSI at 4 MHz
STM32L431xx Functional overview Table 5.Functic onalities depending on the working mode) Stop 0/1 Stop 2 Standby shutdown Peripheral Run VBAT CPU Y SRAM1 (48 KB) SRAM2 (16 KB) (3) 04 Quad SPl Backup Registers Y 0 0 0 0 0 0 DMA 00 0 0 0 Oscillator RC48 0 Speed Exlernal 0 Speed Intemal 0 0 0 Low Speed External 0 (MSD Speed Intema 0 0 0 0 0 0 0 0 0 0 00 RTC/Auto wakeup 0 0 0 0 0 0000 0 Number of RTC 3 3 3 3 USARTx (x=1.2,3) 0 0 0 7 DS11453 Rev 3 29/208
DS11453 Rev 3 29/208 STM32L431xx Functional overview 54 Table 5. Functionalities depending on the working mode(1) Peripheral Run Sleep Lowpower run Lowpower sleep Stop 0/1 Stop 2 Standby Shutdown VBAT - Wakeup capability - Wakeup capability - Wakeup capability - Wakeup capability CPU Y - Y - - - - - - - - - - Flash memory (up to 256 KB) O(2) O(2) O(2) O(2) - - - - - - - - - SRAM1 (48 KB) Y Y(3) Y Y(3) Y - Y - - - - - - SRAM2 (16 KB) Y Y(3) Y Y(3) Y - Y - O(4) - - - - Quad SPI O O O O - - - - - - - - - Backup Registers Y Y Y Y Y - Y - Y - Y - Y Brown-out reset (BOR) Y Y Y YY Y Y Y Y Y - - - Programmable Voltage Detector (PVD) O O O OO O O O - - - - - Peripheral Voltage Monitor (PVMx; x=1,3,4) O O O OO O O O - - - - - DMA O O O O - - - - - - - - - High Speed Internal (HSI16) OOOO (5) - (5) - - - - - - Oscillator RC48 O O - - - - - - - - - - - High Speed External (HSE) O O O O- - - - - - - - - Low Speed Internal (LSI) O O O OO - O - O - - - - Low Speed External (LSE) O O O OO - O - O - O - O Multi-Speed Internal (MSI) O O O O- - - - - - - - - Clock Security System (CSS) O O O O- - - - - - - - - Clock Security System on LSE O O O OO O O O O O - - - RTC / Auto wakeup O O O O O O O O O O O O O Number of RTC Tamper pins 3 3 3 33 O 3 O 3 O 3 O 3 USARTx (x=1,2,3) O O O O O(6) O(6) - - - - - - -
Functional overview STM32L431xx Table 5 Functionalities de ding on the working mode(1)(continued) Stop 0/1 Stop 2 Standby Shutdown SSE Peripheral Run Sleep power gede dne VBAT LPUART UART 0 0 0 0 12Cxx=1.2 0 0 00m0 12C3 0 0 )o(7 o(7)o(. SPx(x=1.2.3) 0 0 CAN SDMMC1 0 0 0 SWPMI1 0 0 0 0 SAlx (x=1) 0 0 ADCx (x=1) 0 0 0 0 DAC1 0 0 0 VREFBUF 0 0 OPAMPx (x=1) 0 0 0 0 0 COMPx (x=1.2) 0 00 00 Temperature sensor 0 Timers(TIMx) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wgatcandeg 0 0 0 SysTick timer 0 0 0 0 0 Rand(RNG) CRC calculation unit 0 0 0 GPIOs 0 0 0 (11) 30/208 DS11453 Rev 3 7
Functional overview STM32L431xx 30/208 DS11453 Rev 3 Low-power UART (LPUART) O O O OO(6) O(6) O(6) O(6) - - - - - I2Cx (x=1,2) O O O O O(7) O(7) - - - - - - - I2C3 O O O O O(7) O(7) O(7) O(7) - - - - - SPIx (x=1,2,3) O O O O - - - - - - - - - CAN O O O O - - - - - - - - - SDMMC1 O O O O - - - - - - - - - SWPMI1 O O O O - O - - - - - - - SAIx (x=1) O O O O - - - - - - - - - ADCx (x=1) O O O O - - - - - - - - - DAC1 O O O O O - - - - - - - - VREFBUF O O O O O - - - - - - - - OPAMPx (x=1) O O O O O - - - - - - - - COMPx (x=1,2) O O O O O O O O - - - - - Temperature sensor O O O O - - - - - - - - - Timers (TIMx) O O O O - - - - - - - - - Low-power timer 1 (LPTIM1) O O O OO O O O - - - - - Low-power timer 2 (LPTIM2) O O O OO O - - - - - - - Independent watchdog (IWDG) O O O OO O O O O O - - - Window watchdog (WWDG) O O O O- - - - - - - - - SysTick timer O O O O - - - - - - - - - Touch sensing controller (TSC) O O O O- - - - - - - - - Random number generator (RNG) O(8) O(8) - -- - - - - - - - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 5 pins (10) (11) 5 pins (10) - Table 5. Functionalities depending on the working mode(1) (continued) Peripheral Run Sleep Lowpower run Lowpower sleep Stop 0/1 Stop 2 Standby Shutdown VBAT - Wakeup capability - Wakeup capability - Wakeup capability - Wakeup capability