Functional overview STM32L431xx 3.12 General-purpose inputs/outputs(GPIOs) nate functions.Fast O toggling can be The l/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the l/Os registers. 3.13 Direct memory access controller(DMA) The device embeds 2 DMAs.Refer to Table 7:DMA implementation for the features implementation. Direct memory access (DMA)is used in order to provide high-speed data transfer between requests The DMA supports: 14 independently configurable channels (requests) Each channel is connected to dedicated hardware DMA requests.software trigger is also supported on each channel.This configuration is done by software. ery high.high,med aengndpac3g2s6egegnhanornoeoeaeagednmeamd size. Support for circular buffer management 3scs8g9emaeopeca68em2DmaaneEnon Memory-to-memory transter fasnses3lonenoynnenortopepelsnNpeapneaoopeal Access to Flash,SRAM,APB and AHB peripherals as source and destination Programmable number of data to be transferred:up to 65536. Table 7.DMA implementation DMA features DMA1 DMA2 Number of regular channels 7 7 36/208 DS11453 Rev 3 7
Functional overview STM32L431xx 36/208 DS11453 Rev 3 3.12 General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.13 Direct memory access controller (DMA) The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features implementation. Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests. The DMA supports: • 14 independently configurable channels (requests) • Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management • 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers • Access to Flash, SRAM, APB and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65536. Table 7. DMA implementation DMA features DMA1 DMA2 Number of regular channels 7 7
STM32L431xx Functional overview 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller(NVIC) M4. The nvic benefits are the following ow latency inte Allows early processing of interrupts Proces ng of late arriving higher priority interrupts Support for tail chaining Processor state automatically saved on interrupt entry.and restored on interrupt exit. with no instruction overheac The NVIC hardware block provides flexible interrupt management features with minimal nterrupt latency. 3.14.2 Extended interrupt/event controller(EXTI) The exte ntroller consists of 37 e elect the trigger ev eage edge.bo oth)and ca the internal clock period.Up nterrupt lines 7 DS11453 Rev 3 371208
DS11453 Rev 3 37/208 STM32L431xx Functional overview 54 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex®- M4. The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.14.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 37 edge detector lines used to generate interrupt/event requests and wake-up the system from Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 83 GPIOs can be connected to the 16 external interrupt lines
Functional overview STM32L431xx 3.15 Analog to digital converter(ADC) nstasucasneapocnaionnogodgaonetgwhe The device 12-it native resolution,with built-in calibration 5.33 Msps m n rate with full resolution conversion rate for lower(up to.88 Msps for 6-bit Up to 16 ext emal channels 。 One exte Single-ended and differential mode inputs ·Low-power design Capable of low-c linearly with speed) ent operation at low conversion rate(consumption decreases Dual clock domain architecture:ADC speed independent from CPU frequency Highly versatile digital interface Single-shot or continuous/discontinuous sequencer-based scan mode:2 a UDS of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions ADC supports multiple trigger inputs for synchronization with on-chip timers and Results stored into datare or in RAM with DMA Data pre-processing:left/right alignment and per channel offset compensation Built-in oversampling unit for enhanced SNR Channel-wise programmable sampling time Three analog watchdog for automatic voltage monitoring,generating interrupts and trigger fo angrmtioprepareheonieaotnenetedchanmestoaowths elected timers Hardware assis 3.15.1 Temperature sensor The temperature sensor(TS)generates a voltage VTs that varies linearly with temperature. The te ected to the ADC1_IN17 input channel which is The ser tomchigiochipduetoprocessvanaionhencatratedntemaltemperauresensorts suitable for applications that detect temperature changes only. To improve the accuracy of the te eST.The temperature sensor factory calibration data individually factory-calibr libration data are only mode. 38/208 DS11453 Rev 3 7
Functional overview STM32L431xx 38/208 DS11453 Rev 3 3.15 Analog to digital converter (ADC) The device embeds a successive approximation analog-to-digital converter with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution – Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 16 external channels. • 5 internal channels: internal reference voltage, temperature sensor, VBAT/3, DAC1_OUT1 and DAC1_OUT2. • One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply • Single-ended and differential mode inputs • Low-power design – Capable of low-current operation at low conversion rate (consumption decreases linearly with speed) – Dual clock domain architecture: ADC speed independent from CPU frequency • Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions – ADC supports multiple trigger inputs for synchronization with on-chip timers and external signals – Results stored into data register or in RAM with DMA controller support – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast context switching 3.15.1 Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN17 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode
STM32L431xx Functional overview Table 8.Temperature sensor calibration values Calibration value name Description Memory address TS_CAL1 0x1FFF 75A8-0x1FFF 75A9 VDo=VREE+=3.0V(t 10 mV) TS ADC raw data acquired at a TS_CAL2 3.0v4i0m 0x1FFF 75CA-0x1FFF 75CB 3.15.2 Internal voltage reference(VREFINT) The teal votRFINT)rvidstaol oupuor the ADC and Comparators.VR of to th for during production test and stored in the system memory area.Itis accessible in readonly mode. Table 9.Internal voltage reference calibration values Calibration value name Description Momory addross Raw data acquired at a VREFINT 0x1FFF 75AA-0x1FFF 75AB R日F+ 3.15.3 VeAr battery voltage monitoring anseaw uoda outside the divider by 3.As a consequence.the converted digital value is one third the Vr voltage. 3.16 Digital to analog converter(DAC) 7 DS11453 Rev 3 39208
DS11453 Rev 3 39/208 STM32L431xx Functional overview 54 3.15.2 Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. 3.15.3 VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN18. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third the VBAT voltage. 3.16 Digital to analog converter (DAC) Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. Table 8. Temperature sensor calibration values Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB Table 9. Internal voltage reference calibration values Calibration value name Description Memory address VREFINT Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75AA - 0x1FFF 75AB
Functional overview STM32L431xx Thisdigialiniteracesuppotstheolorwimgfeatures Jp to two DAC o annels Buffer offset calibration(factory and user trimming) Left or right data alignment in 12-bit mode Synchronized update capability Noise-wave generation Trianaular-wave generation Dual DAC channel independent or simultaneous conversions DMA capability for each channel Exte O820Cbaea0ea9edtrogtetnrptaao2ostaa03comnece 3.17 Voltage reference buffer(VREFBUF) pin The internal voltage reference buffer supports two voltages: ·2.048V 。2.5V can be provided through the VREF+pin when the intema Figure 5.Voltage reference buffer VREFBUF DA C.ADC dga 40/208 DS11453 Rev 3 7
Functional overview STM32L431xx 40/208 DS11453 Rev 3 This digital interface supports the following features: • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-power mode, with internal or external capacitor The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.17 Voltage reference buffer (VREFBUF) The STM32L431xx devices embed an voltage reference buffer which can be used as voltage reference for ADCs, DAC and also as voltage reference for external components through the VREF+ pin. The internal voltage reference buffer supports two voltages: • 2.048 V • 2.5 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available. Figure 5. Voltage reference buffer MSv40197V1 VREFBUF Low frequency cut-off capacitor DAC, ADC Bandgap + VDDA - 100 nF VREF+