STM32L431xx Functional overview Figure 2.Power supply overview MO ring P86eeandpoertonphes.tetoohmgpowergaqenaeeuremens When Voo is above 1V.all power supplies are independent. During the power-down phase.Voo can temporarily become lower than other supplies only ith ienensbeoewnsnsalgeepeealdscPansent ning the power-ao phase. 7 DS11453 Rev 3 21/208
DS11453 Rev 3 21/208 STM32L431xx Functional overview 54 Figure 2. Power supply overview During power-up and power-down phases, the following power sequence requirements must be respected: • When VDD is below 1 V, other power supplies (VDDA) must remain below VDD + 300 mV. • When VDD is above 1 V, all power supplies are independent. During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ; this allows external decoupling capacitors to be discharged with different time constants during the power- down transient phase. MSv39205V2 Low voltage detector VDDA VDDA domain VSS VDD VBAT A/D converters Comparators D/A converters Operational amplifiers Voltage reference buffer VDD domain I/O ring VSSA Reset block Temp. sensor PLL, HSI, MSI, HSI48 Standby circuitry (Wakeup logic, IWDG) Voltage regulator VDDIO1 LSE crystal 32 K osc BKP registers RCC BDCR register RTC Backup domain Core Memories Digital peripherals VCORE domain VCORE
Functional overview STM32L431xx Figure 3.Power-up/down sequence ower-o Operating mod ower-dow □aax<vem+300mv Vox independent from Vo S47490 Vpox refers to VpoA 3.9.2 Power supply supervisor The de specified threshold,without the need for an external reset circuit. The lowest boR level is 171V at power on.and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector In addition.the device embeds a Peripheral Voltage Monitor which compares the independent supply voltage VoDA with a fixed threshold in order to ensure that the peripheral is in its functional supply range. 221208 DS11453 Rev 3 司
Functional overview STM32L431xx 22/208 DS11453 Rev 3 Figure 3. Power-up/down sequence 1. VDDX refers to VDDA. 3.9.2 Power supply supervisor The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down. The device remains in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the device embeds a Peripheral Voltage Monitor which compares the independent supply voltage VDDA with a fixed threshold in order to ensure that the peripheral is in its functional supply range. MSv47490V1 0.3 1 VBOR0 3.6 Power-on Power-down time Operating mode V VDDX(1) VDD Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
STM32L431xx Functional overview 3.9.3 Voltage regulator Two embedded rgulators supply most of the digital circuitries:the main regulator(MR)and the low-power regulator(LPR). The MR is used in the Run and Sleep modes and in the Stop 0 mode The LPR is used in Low-Power Run,Low-Power Sleep,Stop 1 and Stop 2 modes.It is also used to supply the 16 Kbyte SRAM2 in Standby with SRAM2 retention. Both requlators are in power-down in Standby and Shutdown modes:the regulator output is in high impedance,and the kernel circuitry is powered down thus inducing zero consumption The ultralow-power STM32L431xx supports dynamic voltage scaling to optimize its power consumption in run mode.The voltage from the Main Regulator that supplies the logic (VCoRE)can be adjusted according to the system's maximum operating frequency. There are two power consumption ranges: Range 1 with the CPU running at up to 80 MHz. Range 2 with a maximum CPU frequency of 26 MHz.All peripheral clocks are also limited to 26 MHz. The VcoRE can be supplied by the low-power regulator,the main regulator being switched off.The system is then in Low-power run mode. Low-power run mode with the CPU running at up to 2 MHz.Peripherals with independent clock can be clocked by HS116. 3.9.4 Low-power modes The ultra-low-power STM32L431xx supports seven low-power modes to achieve the best compromise between low-power consumption,short startup time,available peripherals and available wakeup sources. 7 DS11453 Rev 3 23/208
DS11453 Rev 3 23/208 STM32L431xx Functional overview 54 3.9.3 Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 16 Kbyte SRAM2 in Standby with SRAM2 retention. • Both regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. The ultralow-power STM32L431xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency. There are two power consumption ranges: • Range 1 with the CPU running at up to 80 MHz. • Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also limited to 26 MHz. The VCORE can be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode. • Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by HSI16. 3.9.4 Low-power modes The ultra-low-power STM32L431xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources
Table 4.STM32L431xx modes overview Mode CPU FlashSRAM Clocks DMA&Peripherals(2 Wakeup sourco Consumption(3)Wakeup time e MR range 1 Yes ON() 9% A Any NA 97uAWM电 NIA MR range2 All except RNG 84 UA/MHz LPRu LPR Yes ON ON All except USB FS.RNG NA 94uAM位 to Range 1:4 us o Range 2:64 us MR range 1 ON 28μAMHz Any 6 cycles MR range2 All except RNG 26uAM位 LPSlee LPR No ON(4 All except USB_FS.RNG 29μAMH也 6 cycles 9S11463R03 BOR,PVD.PVM MR Range 1 108A DAC1 No OFF ON 2Cx6x=13j网 PUART1间 2s LPTIMx (x1.2) 2Cxe13)7 MR Range 2 SWPM1 108A All other peripherals are frozen
24/208 DS11453 Rev 3 Functional overview STM32L431xx Table 4. STM32L431xx modes overview Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time Run MR range 1 Yes ON(4) ON Any All N/A 97 µA/MHz N/A MR range2 All except RNG 84 µA/MHz LPRun LPR Yes ON(4) ON Any except PLL All except USB_FS, RNG N/A 94 µA/MHz to Range 1: 4 µs to Range 2: 64 µs Sleep MR range 1 No ON(4) ON(5) Any All Any interrupt or event 28 µA/MHz 6 cycles MR range2 All except RNG 26 µA/MHz LPSleep LPR No ON(4) ON(5) Any except PLL All except USB_FS, RNG Any interrupt or event 29 µA/MHz 6 cycles Stop 0 MR Range 1 No OFF ON LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1) USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) SWPMI1(8) 108 µA 2.4 µs in SRAM 4.1 µs in Flash MR Range 2 108 µA
Table 4.STM32L431xx modes overview (continued) Mode Regulator(1) CPU Flash SRAM Clocks DMA&Peripherals(☒ Wakeup source Consumption周 Wakeup time BOR,PVD,PVM RTC.IWDG Reset pin,all /Os STM32L431xx COMPx(x=1.2) BOR PVD PVM DAC1 RTC.IWDG OPAMPx (x=1) USARTx(x=1...3)(6) COMPx (x=1..2) Stop1 LPR No ON 4.34μAwo RTC 6.3 us in SRAM LPUART1何 USARTx(x=1...3)(6) LPUART1(6) 4.63μAw RTC 7.8 us in Flash 2Cx(x=1.3) 2Cx(x=13) LPTIMx (x=1.2) LPTIMx (x=1,2) SWPMI1(8) All other peripherals are frozen. BOR,PVD,PVM DS11453R0 RTC,IWDG Reset pin,all l/Os COMPx (x=1..2) BOR.PVD.PVM 2C30 RTC.IWDG Stop2 LPR No Of ON LPUART1同 COMPx(x=1.2) 1.3μAwlo RTC 6.8 us in SRAM 2c3 1.4μAw/RTC 8.2 us in Flash LPTIM1 LPUART1间) LPTIM1 252/208 Functional overview
STM32L431xx Functional overview DS11453 Rev 3 25/208 Stop 1 LPR No Off ON LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1) USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) USARTx (x=1...3)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) SWPMI1(8) 4.34 µA w/o RTC 4.63 µA w RTC 6.3 µs in SRAM 7.8 µs in Flash Stop 2 LPR No Off ON LSE LSI BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) I2C3(7) LPUART1(6) LPTIM1 *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, IWDG COMPx (x=1..2) I2C3(7) LPUART1(6) LPTIM1 1.3 µA w/o RTC 1.4 µA w/RTC 6.8 µs in SRAM 8.2 µs in Flash Table 4. STM32L431xx modes overview (continued) Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time