Description STM32L431xx Figure 1.STM32L431xx block diagram aa Note: AF:alternate function on VO pins 16/208 DS11453 Rev 3 7
Description STM32L431xx 16/208 DS11453 Rev 3 Figure 1. STM32L431xx block diagram Note: AF: alternate function on I/O pins. MSv39204V2 Flash up to 256 KB GPIO PORT A AHB/APB2 83 AF EXT IT. WKUP PA[15:0] TIM1 / PWM 3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF RX, TX, CK,CTS, USART1 RTS as AF SPI1 MOSI, MISO, SCK, NSS as AF APB2 60 M Hz A P B 1 3 0M Hz OUT1 ITF WWDG RTC_TS OSC32_IN OSC32_OUT smcard IrDA 16b SDIO / MMC D[7:0] CMD, CK as AF VBAT = 1.55 to 3.6 V JTAG & SW ARM Cortex-M4 80 MHz FPU ETM NVIC MPU DMA2 ART ACCEL/ CACHE RNG FIFO @ VDDA BOR Supply supervision PVD, PVM Int reset XTAL 32 kHz M AN A G T RTC FCLK Standby interface IWDG @VBAT @ VDD @VDD AWU Reset & clock control PCLKx Voltage regulator 3.3 to 1.2 V VDD Power management @ VDD RTC_TAMPx Backup register AHB bus-matrix TIM15 2 channels, 1 compl. channel, BKIN as AF DAC1 DAC2 TIM6 TIM7 TIM2 D-BUS SRAM 48 KB APB1 80 MHz (max) SRAM 16 KB I-BUS S-BUS DMA1 PB[15:0] PC[15:0] PD[15:0] PE[15:0] PH[1:0], PH[3] GPIO PORT B GPIO PORT C GPIO PORT D GPIO PORT E GPIO PORT H 16b TIM16 16b 1 channel, 1 compl. channel, BKIN as AF OUT2 16b 16b 32b 4 channels, ETR as AF AHB/APB1 OSC_IN OSC_OUT HCLKx XTAL OSC 4- 16MHz 16 external analog inputs VREF+ U S AR T 2 M B p s Temperature sensor @ VDDA SAI1 MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF Touch sensing controller 7 Groups of 3 channels max as AF RC HSI RC LSI PLL 1&2 MSI Quad SPI memory interface D0[3:0], D1[3:0], CLK0, CLK1 CS INP, INM, OUT COMP1 INP, INM, OUT COMP2 @ VDDA RTC_OUT AHB1 80 MHz CRC APB2 80MHz AHB2 80 MHz FIREWALL VREF Buffer @ VDDA @ VDD VDD = 1.71 to 3.6 V VSS TRACECLK TRACED[3:0] NJTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO ADC1 ITF HSI48 VDDA, VSSA VDD, VSS, NRST CRS CRS_SYNC USART2 RX, TX, CK, CTS, RTS as AF smcard IrDA USART3 smcard RX, TX, CK, CTS, RTS as AF IrDA SPI2 MOSI, MISO, SCK, NSS as AF SPI3 MOSI, MISO, SCK, NSS as AF I2C1/SMBUS SCL, SDA, SMBA as AF I2C2/SMBUS SCL, SDA, SMBA as AF I2C3/SMBUS SCL, SDA, SMBA as AF FIFO bxCAN1 TX, RX as AF OpAmp1 VOUT, VINM, VINP @VDDA LPUART1 RX, TX, CTS, RTS as AF SWPMI1 IO RX, TX, SUSPEND as AF LPTIM1 IN1, IN2, OUT, ETR as AF LPTIM2 IN1, OUT, ETR as AF
STM32L431xx Functional overview 3 Functional overview 3.1 Arm®Cortex®-M4 core with FPU The Arm Cortex-M4 with FPU processor is the latest generation of Arm processors for asdeveloped to provide a -cost platform that meets the needs of usually associated with 8and 16-pit devices. mory size TepegarsneeanonlofosPnstncionswhchalowesicenlsgnalprocesingand speds up development by using metalanguage voiding satura With its embedded Arm core,the STM32L431xx family is compatible with all Armtools Figure 1 shows the general block diagram of the STM32L431xx family devices. 3.2 Adaptive real-time memory accelerator(ART AcceleratorTM) To release the processor near 100 DMIPS performance at 80MHz,the accelerator the 64-it performance ach ed thanks to the ARTacc elerator is e romFlash memory at a CPU frequency up toMnt to o wait state program exec 3.3 Memory protection unit The memory protection unit(MPU)is used to manage the CPU accesses to mem ory to eas thaed up into8 subareas.The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be poectedgansthemeehaorofothnertasmesmsvaamgnaignRTCa5ye emel can dynamically update the MPU area setting.based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 7 DS11453 Rev 3 17208
DS11453 Rev 3 17/208 STM32L431xx Functional overview 54 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm® core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded Arm® core, the STM32L431xx family is compatible with all Arm® tools and software. Figure 1 shows the general block diagram of the STM32L431xx family devices. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor near 100 DMIPS performance at 80MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it
Functional overview STM32L431xx 3.4 Embedded Flash memory pages of Kpyte. Level 0:no readout protectior Heeniomreom2reoggnesometbenlaeiameo8rYnandt。e0aemgi Level 2:chip readout protection:debug features(Cortex-M4 JTAG and serial erelbagneMnebotoa3derseectonaredsabiedUTAGselThs Table 3.Access status versus readout protection level and execution modes User execution Area Read Write Erase Read Write Erase Yes Yes No 2 Yes Yes Yes N/A N/A NA Yes No No No No 2 Yes No No N/A N/A N/A e Yes Yes Yes Yes Yes Yes No NIA NIA 1 Yes Yes N/AG No No N/A 2 Yes Yes N/A N/A NIA SRAMZ Yes Yes Yes仞 No No(1) 2 Yes Yes Yes N/A N/A N/A Frased when RDP change from Level 1 to Level 0 Write protection (WRP):the protected area is protected against erasing and programming.Two areas can be selected,with 2-Kbyte granularity. Proprietary code readout protection(PCROP):a part of the flash memory can be STM32 CPU.as an inst only all othe ad.write and erase)are strictly prohib area gra tion iDP) changed from Level 1 to Level 0. 18/208 DS11453 Rev 3 7
Functional overview STM32L431xx 18/208 DS11453 Rev 3 3.4 Embedded Flash memory STM32L431xx devices feature up to 256 Kbyte of embedded Flash memory available for storing programs and data in single bank architecture. The Flash memory contains 128 pages of 2 Kbyte. Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected – Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible. • Write protection (WRP): the protected area is protected against erasing and programming. Two areas can be selected, with 2-Kbyte granularity. • Proprietary code readout protection (PCROP): a part of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. Table 3. Access status versus readout protection level and execution modes Area Protection level User execution Debug, boot from RAM or boot from system memory (loader) Read Write Erase Read Write Erase Main memory 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A System memory 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A Option bytes 1 Yes Yes Yes Yes Yes Yes 2 Yes No No N/A N/A N/A Backup registers 1 Yes Yes N/A(1) 1. Erased when RDP change from Level 1 to Level 0. No No N/A(1) 2 Yes Yes N/A N/A N/A N/A SRAM2 1 Yes Yes Yes(1) No No No(1) 2 Yes Yes Yes N/A N/A N/A
STM32L431xx Functional overview The whole non-volatile memory embeds the error correction code(ECC)feature supporting Single erro dete The address of the ECC fail can be read in the ECC register 3.5 Embedded SRAM devces featureKbyle ofmdR ThsMw 48 Kbyte mapped at(SRAM1) 16 Kbyte located at address Ox1000 0000 with hardware parity check(SRAM2). pem2Ye5sks0Mm28elgais,020nGg0.oienmgaconiguousadtres The SRAM2 can be write-protected with 1 Kbyte granularity. The memory can be accessed in read/write at CPU clock speed with 0 wait states. 3.6 Firewall The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. Each illegal access generates a reset which kills immediately the detected intrusion The Firewall main features are the follo wing: cocegegtscanbeprot s to the Firewall segment( eal Non-volatile data segment (located in Flash) Volatile data seament (located in SRAM1) The start address and the length of each segments are configurable Code segment:up to 1024 Kbyte with granularity of 256 bytes Non-volatile data segment:up to 1024 Kbyte with granularity of 256 bytes Volatile data segment:up to 48 Kbyte with a granularity of 64 bytes Specific mechanism implemented to open the Firewall to get access to the protected s (ce I gate entry sequence) e ta segment ca an be shared or not with the non-prot d code 。 Volatile data segment can be executed or not depending on the Firewall configuration The Flash readout protection must be set to level 2 in order to reach the expected level of protection. 7 DS11453 Rev 3 19208
DS11453 Rev 3 19/208 STM32L431xx Functional overview 54 The whole non-volatile memory embeds the error correction code (ECC) feature supporting: • single error detection and correction • double error detection. • The address of the ECC fail can be read in the ECC register 3.5 Embedded SRAM STM32L431xx devices feature 64 Kbyte of embedded SRAM. This SRAM is split into two blocks: • 48 Kbyte mapped at address 0x2000 0000 (SRAM1) • 16 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2). This memory is also mapped at address 0x2000 C000, offering a contiguous address space with the SRAM1 (16 Kbyte aliased by bit band) This block is accessed through the ICode/DCode buses for maximum performance. These 16 Kbyte SRAM can also be retained in Standby mode. The SRAM2 can be write-protected with 1 Kbyte granularity. The memory can be accessed in read/write at CPU clock speed with 0 wait states. 3.6 Firewall The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. Each illegal access generates a reset which kills immediately the detected intrusion. The Firewall main features are the following: • Three segments can be protected and defined thanks to the Firewall registers: – Code segment (located in Flash or SRAM1 if defined as executable protected area) – Non-volatile data segment (located in Flash) – Volatile data segment (located in SRAM1) • The start address and the length of each segments are configurable: – Code segment: up to 1024 Kbyte with granularity of 256 bytes – Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes – Volatile data segment: up to 48 Kbyte with a granularity of 64 bytes • Specific mechanism implemented to open the Firewall to get access to the protected areas (call gate entry sequence) • Volatile data segment can be shared or not with the non-protected code • Volatile data segment can be executed or not depending on the Firewall configuration The Flash readout protection must be set to level 2 in order to reach the expected level of protection
Functional overview STM32L431xx 3.7 Boot modes AeatlnorOpmnnSN8oT0optonbtanBor1opionbaetsedtose Boot from user Flash om system emory Boot from embedded SRAM BOOTO value may come from the PH3-BOOTO pin or from an option bit depending on the value of a user option bit to free the GPlO pad if needed. f6tmhnssnylocaionsnotprogrammedanmfhetois0iechonsCogeahbboe A Flash empty check mechanism is implemented to force the boot from system flash if the first flash n The boot loader is located in system memory.It is used to reprogram the Flash memory by using USART.12C.SPI or CAN 3.8 Cyclic redundancy check calculation unit(CRC) The CRC(cyclic redundancy check)calculation unit is used to get a CRC code using a configurable generator polynomial value and size. used to verify data transmissio n or d0sgmenmo%n6e8eoTmpeCcwmaleeenetepcpeaegamtR.o time and stored at a given memory location. 3.9 Power supply management 3.9.1 Power supply schemes Vpp=1.71 to 3.6 V:extemnal power supply for l/Os (Vp )the intemal regulator and the syster rmanagmnnmprovid VDD pins /1.8(DA C/OP voltage level is independent from the voltage. V.o 3.6V p15a36Moamgosergfrea0ack2osaaora Note When the functions supplied by not used,this supply should preferably be shorted to VoD Note. ed by these power supplies are not 5 Note: VpDrox is the lOs general purpose digital functions supply.Vpplox represents VpDo1.with DDIO1 VDD- 20/208 DS11453 Rev 3 7
Functional overview STM32L431xx 20/208 DS11453 Rev 3 3.7 Boot modes At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed. A Flash empty check mechanism is implemented to force the boot from system flash if the first flash memory location is not programmed and if the boot selection is configured to boot from main flash. The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI or CAN. 3.8 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.9 Power supply management 3.9.1 Power supply schemes • VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins. • VDDA = 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMP) to 3.6 V: external analog power supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The VDDA voltage level is independent from the VDD voltage. • VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Note: When the functions supplied by VDDA are not used, this supply should preferably be shorted to VDD. Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant (refer to Table 19: Voltage characteristics). Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1, with VDDIO1 = VDD