VHDL语言中并行语句有 并行信号赋值语句 ● Process语句 ●并行程序( procedure)调用 ●并行断言( assertion)语句 ● Block语句 →●元件实例化语句 ● Generate语句
VHDL语言中并行语句有 语言中并行语句有 z 并行信号赋值语句 z Process语句 z 并行程序（procedure)调用 z 并行断言（assertion)语句 z Block语句 z 元件实例化语句 z Generate语句
Block语句 Block语句是分解硬件功能的主要的 并行语句。它将多个并行语句归入一个 设计单元
一、Block语句 Block语句是分解硬件功能的主要的 并行语句。它将多个并行语句归入一个 设计单元
格式: block statement abe BLOCK(expression) block declarative item BEGIN concurrent statement END BLOCK label
格式： block statement …… label: BLOCK (expression) block_declarative_item BEGIN concurrent_statement END BLOCK label;
AS]: ENTITY bistable latch IS PORT(enable, data: IN bit q,q not oUt bit) end bistable latch
例：ENTITY bistable_latch IS PORT (enable, data : IN bit; q, q_not : OUT bit); END bistable_latch;
ARCHITECTURE example of bistable latch Is BEGIN latch BLOCK(enable=1) siGnaL d in: bit BEGIN guarded data q d q not < not d in END BLOCK latch END example
ARCHITECTURE example OF bistable_latch IS BEGIN latch1: BLOCK (enable=‘1’) SIGNAL d_in : bit; BEGIN d_in <= GUARDED data; q <= d_in; q_not <= NOT d_in; END BLOCK latch1; END example;