DRAMControllers: A row-conflict memory access takes significantly longerthan a row-hit access. Current controllers take advantage of the row buffer Commonly used scheduling policy (FR-FCFS)(1) Row-hit first: Service row-hit memory accesses first(2) Oldest-first: Then service older accesses firstThis scheduling policy aims to maximize DRAMthroughputComputerArchitecture11
Computer Architecture DRAM Controllers • A row-conflict memory access takes significantly longer than a row-hit access • Current controllers take advantage of the row buffer • Commonly used scheduling policy (FR-FCFS) (1) Row-hit first: Service row-hit memory accesses first (2) Oldest-first: Then service older accesses first • This scheduling policy aims to maximize DRAM throughput 11
TheProblem: Multiple threads share the DRAM controllerDRAM controllers designed to maximize DRAMthroughput. DRAM scheduling policies are thread-unfair- Row-hit first: unfairly prioritizes threads with high row buffer locality: Threads that keep on accessing the same row- Oldest-first: unfairly prioritizes memory-intensive threadsDRAM controller vulnerable to denial of serviceattacks- Can writeprograms to exploit unfairnessComputerArchitecture12
Computer Architecture The Problem • Multiple threads share the DRAM controller • DRAM controllers designed to maximize DRAM throughput • DRAM scheduling policies are thread-unfair – Row-hit first: unfairly prioritizes threads with high row buffer locality • Threads that keep on accessing the same row – Oldest-first: unfairly prioritizes memory-intensive threads • DRAM controller vulnerable to denial of service attacks – Can write programs to exploit unfairness 12
AMemoryPerformanceHogIl initialize large arrays A, BIl initialize large arrays A, Bfor (j=0; j<N; j++)for (i=0; j<N; j++) (index =j*linesize;index = randO;streamingrandomA[index] = B[index]A[index] = B[index];RANDOMSTREAM-Sequentialmemoryaccess-Randommemoryaccess- Very high row buffer locality (96% hit rate) - Very low row buffer locality (3% hit rate)-Memoryintensive-SimilarlymemoryintensiveComputerArchitecture13
Computer Architecture // initialize large arrays A, B for (j=0; j<N; j++) { index = rand(); A[index] = B[index]; . } A Memory Performance Hog UVTGCO" - Sequential memory access - Very high row buffer locality (96% hit rate) - Memory intensive TCPFQO" - Random memory access - Very low row buffer locality (3% hit rate) - Similarly memory intensive // initialize large arrays A, B for (j=0; j<N; j++) { index = j*linesize; A[index] = B[index]; . } uvtgcmkpi" tcpfqm 13
What Does the Memory Hog Do?TO:Row 0TO: Row 5T10:ROoM01To:RaW16MemoryRequestBufferRowBufferRowsize:8KB,cacheblocksize:64B128 (8KB/64B) requests of T0 serviced before T1ComputerArchitecture14
Computer Architecture What Does the Memory Hog Do? Row Buffer Row decoder Column mux Data Row 0 T0: Row 0 Row 0 T1: Row 16 T1: Row 111 T0: Row 0 T0: Row 0 T1: Row 5 T0: Row 0 Memory Request Buffer T0: STREAM T1: RANDOM Row size: 8KB, cache block size: 64B 128 (8KB/64B) requests of T0 serviced before T1 14
NowThatWeKnowWhatHappensUnderneathHowwould you solvetheproblem?. What is the right place to solve the problem?- Programmer?Problem-System software?Algorithm-Compiler?Program/Language- Hardware (Memory controller)?RuntimeSystem-Hardware (DRAM)?(VM,OS,MM)- Circuits?ISA (Architecture)MicroarchitectureTwo other goals of this course:- Make you think criticallyCircuits- Make you think broadlyElectronsComputerArchitecture15
Computer Architecture Now That We Know What Happens Underneath • How would you solve the problem? • What is the right place to solve the problem? – Programmer? – System software? – Compiler? – Hardware (Memory controller)? – Hardware (DRAM)? – Circuits? • Two other goals of this course: – Make you think critically – Make you think broadly Microarchitecture ISA (Architecture) Program/Language Algorithm Problem Logic Circuits Runtime System (VM, OS, MM) Electrons 15