AnExample:Multi-CoreSystemsMulti-CoreChipL2CACHEL2CACHESHAREDL3CACHECOREOCORE1DRAM BANKSWne-DRAM MEMORYCONTROLLERRFACE人NCACHECACHECORE3CORE2-乙*Diephotocredit:AMDBarcelonaComputerArchitecture
Computer Architecture EQTG"3" N4"ECEJG"2" UJCTGF"N5"ECEJG" FTCO"KPVGTHCEG" EQTG"2" EQTG"4" EQTG"5" N4"ECEJG"3" N4"ECEJG"4" N4"ECEJG"5" FTCO"DCPMU" Multi-Core Chip *Die photo credit: AMD Barcelona DRAM MEMORY CONTROLLER An Example: Mul4-Core Systems 6
UnexpectedSlowdownsinMulti-CoreHigh priority43.53.043MemoryPerformanceHog2.5Low priorityumopmos21.51.0710.50matlabgcc(Core 0)(Core 1)ComputerArchitecture
Computer Architecture 1.07% 3.04% 0% 0.5% 1% 1.5% 2% 2.5% 3% 3.5% 4% matlab% gcc% Slowdown% Ogmqt{"Rgthqtmcpeg"Jqi" Nqy"rtkqtkv{" Jkij"rtkqtkv{" (Core 0) (Core 1) Unexpected Slowdowns in Mul4-Core 7
AnQuestionorTwo Can you figure out why there is a disparity inslowdowns if you do not know how the processorexecutes the programs? Can you fix the problem without knowing what ishappening"underneath"?ComputerArchitecture
Computer Architecture • Can you figure out why there is a disparity in slowdowns if you do not know how the processor executes the programs? • Can you fix the problem without knowing what is happening “underneath”? An Ques4on or Two 8
Why the Disparity in Slowdowns?Multi-CoregccChipL2L2CACHECACHEunfairness↑HINTERCONNECTSharedDRAMMemorySystemDRAMMEMORYCONTROLLERDRAMDRAMDRAMDRAMBank 3BankoBank 1Bank 2ComputerArchitecture
Computer Architecture Why the Disparity in Slowdowns? CORE 1 CORE 2 L2 CACHE L2 CACHE DRAM MEMORY CONTROLLER DRAM Bank 0 DRAM Bank 1 DRAM Bank 2 Shared DRAM Memory System Multi-Core Chip unfairness INTERCONNECT matlab gcc DRAM Bank 3 9
DRAMBankOperationAccessAddressColumns(Row0,Column0)(Row0,Column1)(Row0.Column85)(Row1,Column0)RowSRowaddress0Row1RowBuffereONFLicT!Column muxColumnaddress@5DataComputerArchitecture10
Computer Architecture DRAM Bank Opera4on Row Buffer (Row 0, Column 0) Row decoder Column mux Row address 0 Column address 0 Data Row 0 Empty (Row 0, Column 1) Column address 1 (Row 0, Column 85) Column address 85 (Row 1, Column 0) HIT Row address 1 Row 1 Column address 0 CONFLICT ! Columns Rows Access Address: 10