高职嵌入式教材配套电子资源（技术资料）STM32L4xx参考手册（RM0394 Reference manual）advanced Arm-based 32-bit MCUs

Contents RM0394 28.5.20 DMA burst mode 921 28.5.21 Timer synchronization (TIM15)..............................923 28.5.22 Debug mode 923 28.6 TIM15 registers 924 28.6.1 TIM15 control register 1 (TIM15 CR1) 924 28.62 TIM15 control register 2(TIM15_CR2) 925 28.6.3 TIM15 slave mode control register (TIM15 SMCR) 927 28.6.4 TIM15 DMA/interrupt enable register (TIM15_DIER) 928 28.6.5 TIM15 status register(TIM15_SR) 28.6.6 TIM15 event generation register(TIM15_EGR) 931 28.6.7 TIM15 capture/compare mode register 1(TIM15_CCMR1) 932 28.6.8 TIM15 capture/compare enable register (TIM15 CCER)......... .936 28.6.9 TIM15 counter (TIM15 CNT) 939 28.6.10 TIM15 prescaler (TIM15_PSC) 93g 28.6.11 TIM15 auto-reload register (TIM15_ARR) 939 286.12 TIM15 repetition counter register (TIM15_RCR) 940 4 28.6.13 TIM15 capture/compare register1(TIM15_CCR1)........... 40 28.6.14 TIM15 capture/compare register 2(TIM15 CCR2) 941 28.6.15 TIM15 break and dead-time register (TIM15_BDTR) 941 28.6.16 TIM15 DMA control register (TIM15 DCR).. 943 286 17 TIM15 DMA address for full transfer (TIM15 DMAR) 944 28.618 TIM15 option register 1(TIM15_OR1).................... 944 28.6.19 TIM15 option register 2 (TIM15_OR2) 945 28 6 20 TIM15 reaister nap 946 28.7 TIM16 registers 949 28.7.1 TIM16 control register 1(TIM16_CR1) 949 28.7.2 TIM16 control register 2(TIM16_CR2) 950 2873 TIM16 DMA/interrupt enable register (TIM16 DIER) 951 287.4 TIM16 status register (TIM16_SR) 952 28.7.5 TIM16 event generation register (TIM16_EGR).... 953 28.7.6 TIM16 capture/compare mode register 1(TIM16_CCMR1) 954 28.7.7 TIM16 capture/compare enable register(TIM16_CCER) 956 28.78 TIM16 counter (TIM16 CNT). 958 287.9 TIM16 prescaler (TIM16_PSC) 959 28.7.10 TIM16 auto-reload register (TIM16 ARR)... 959 287 11 TIM16 repetition counter register (TIM16 RCR) 960 28.7.12 TIM16 capture/compare register 1 (TIM16_CCR1) 960 26/1600 RM0394 Rev4 7

Contents RM0394 26/1600 RM0394 Rev 4 28.5.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 28.5.21 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 28.5.22 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 28.6 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 28.6.1 TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 924 28.6.2 TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 925 28.6.3 TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . . 927 28.6.4 TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . . 928 28.6.5 TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 28.6.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . . 931 28.6.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . . . . 932 28.6.8 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . . 936 28.6.9 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 28.6.10 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 28.6.11 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . . 939 28.6.12 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . . 940 28.6.13 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . . 940 28.6.14 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . . 941 28.6.15 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . . 941 28.6.16 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . . 943 28.6.17 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . . 944 28.6.18 TIM15 option register 1 (TIM15_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . 944 28.6.19 TIM15 option register 2 (TIM15_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . 945 28.6.20 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946 28.7 TIM16 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949 28.7.1 TIM16 control register 1 (TIM16_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 949 28.7.2 TIM16 control register 2 (TIM16_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 950 28.7.3 TIM16 DMA/interrupt enable register (TIM16_DIER) . . . . . . . . . . . . . 951 28.7.4 TIM16 status register (TIM16_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 28.7.5 TIM16 event generation register (TIM16_EGR) . . . . . . . . . . . . . . . . . 953 28.7.6 TIM16 capture/compare mode register 1 (TIM16_CCMR1) . . . . . . . . 954 28.7.7 TIM16 capture/compare enable register (TIM16_CCER) . . . . . . . . . . 956 28.7.8 TIM16 counter (TIM16_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 28.7.9 TIM16 prescaler (TIM16_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959 28.7.10 TIM16 auto-reload register (TIM16_ARR) . . . . . . . . . . . . . . . . . . . . . . 959 28.7.11 TIM16 repetition counter register (TIM16_RCR) . . . . . . . . . . . . . . . . . 960 28.7.12 TIM16 capture/compare register 1 (TIM16_CCR1) . . . . . . . . . . . . . . . 960

RM0394 Contents 28.7.13 TIM16 break and dead-time register(TIM16_BDTR) .961 28.7.14 TIM16 DMA control register (TIM16_DCR). 。。。。。。。 963 28.7.15 TIM16 DMA address for full transfer(TIM16_DMAR)............. 963 28.7.16 TIM16 option register 1(TIM16_OR1) 964 28.7.17 TIM16 option register 2(TIM16_OR2). 28.7.18 TIM16 register map 966 29 Basic timers (TIM6/TIM7)...................................968 29.1 TIM6/TIM7 introduction 968 29.2 TIM6/TIM7 main features.. 968 29.3 TIM6/TIM7 functional description 969 2931 Time-base unit 969 29.3.2 Counting mode 971 29.3.3 UIF bit remapping,................,..,..,..,..,..... 974 29.3.4 Clock source 974 29.3.5 Debug mode 975 29.4 TIM6/TIM7 registers... 975 29.41 TIM6/TIM7 control register 1(TIMx_CR1)............ 96 29.4.2 TIM6/TIM7 control register 2 (TIMx_CR2). 97 29.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER) 977 29.4.4 TIM6/TIM7 status register (TIMx_SR) 978 29.45 TIM6/TIM7 event generation register(TIMx_EGR) 978 29.4.6 TIM6/TIM7 counter (TIMx_CNT) 978 29.4.7TlM6TlM7 prescaler(TIMx PSC)....................... 979 29.4.8 TIM6/TIM7 auto-reload register(TIMx_ARR) 979 29.4 TIM6/TIM7 register map 980 % Low-power timer (LPTIM).................................. ,981 30.1 Introduction 981 30.2 LPTIM main features 981 30 3 LPTIM implementation 981 30.4 LPTIM functional description 982 30.4.1 LPTIM block diagram 982 30.42 LPTIM trigger mapping 983 30.4.3 LPTIM reset and clocks....................................984 30.4.4 Glitch filter .984 RM0394 Rev4 2711600

RM0394 Rev 4 27/1600 RM0394 Contents 43 28.7.13 TIM16 break and dead-time register (TIM16_BDTR) . . . . . . . . . . . . . 961 28.7.14 TIM16 DMA control register (TIM16_DCR) . . . . . . . . . . . . . . . . . . . . . 963 28.7.15 TIM16 DMA address for full transfer (TIM16_DMAR) . . . . . . . . . . . . . 963 28.7.16 TIM16 option register 1 (TIM16_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . 964 28.7.17 TIM16 option register 2 (TIM16_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . 964 28.7.18 TIM16 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 29 Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 29.1 TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 29.2 TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 29.3 TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 29.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 29.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 29.3.3 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 29.3.4 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 29.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 29.4 TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 29.4.1 TIM6/TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . 975 29.4.2 TIM6/TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . 977 29.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . 977 29.4.4 TIM6/TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 978 29.4.5 TIM6/TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . 978 29.4.6 TIM6/TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978 29.4.7 TIM6/TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979 29.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 979 29.4.9 TIM6/TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 30 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 30.2 LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 30.3 LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 30.4 LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982 30.4.1 LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982 30.4.2 LPTIM trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 30.4.3 LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984 30.4.4 Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984

Contents RM0394 30.4.5 Prescaler 985 30.4.6 Trigger multiplexer........................................985 3047 Operating mode ,986 304.8 Timeout function 988 30.4.9 Vaveform generation,,,,,.,,,,,,,,,,,,,,,,,,,,,,,,,, ,989 30.4.10 Register update 30.41 Counter mode 9 30.4.12 Timer enable 9 30.4.13 Timer counter reset 99 30.4.14Enc0 der mode......................................... 30.4.15 Repetition Counter 994 30.4.16 Debug mode 995 30.5 LPTIM low-power modes 996 30.6 LPTIM interrupts........................................... 996 30.7 LPTIM registers ” 997 30.7.1 LPTIM interrupt and status register(LPTIM ISR) 997 30.7.2 LPTIM interrupt clear register(LPTIM_ICR) 999 30.73 LPTIM interrupt enable register(LPTIM_IER) 1000 30.7.4 LPTIM configuration register(LPTIM CFGR) 1002 30.7.5 LPTIM control register(LPTIM_CR) 1004 30.7.6 LPTIM compare register (LPTIM CMP)................... 1006 30.7.7 LPTIM autoreload register (LPTIM ARR) 1006 30.78 LPTIM counter register (LPTIM_CNT) 1007 30.7.9 LPTIM1 option register (LPTIM1 OR) .1007 30.7.10 LPTIM2 option register(LPTIM2_OR) 1008 30.7.11 LPTIM configuration register 2(LPTIM_CFGR2) 100g 30.7.12 LPTIM repetition register (LPTIM RCR) 1009 30.7.13 LPTIM register map 1010 31 Infrared interface (IRTIM) 。。。。。。。。。。。。。。。。。。。。。。。 1012 Independent watchdog(IWDG) 1013 32.1 Introduction 1013 32.2 main features..................................... 1013 32.3 IWDG functional description 1013 32.3.1 VDG block diagram.,........................,...,..1013 3232 Window ontion ..1014 28/1600 RM0394 Rev4 7

Contents RM0394 28/1600 RM0394 Rev 4 30.4.5 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 30.4.6 Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 30.4.7 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986 30.4.8 Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988 30.4.9 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989 30.4.10 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990 30.4.11 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 30.4.12 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 30.4.13 Timer counter reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992 30.4.14 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992 30.4.15 Repetition Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994 30.4.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995 30.5 LPTIM low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996 30.6 LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996 30.7 LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997 30.7.1 LPTIM interrupt and status register (LPTIM_ISR) . . . . . . . . . . . . . . . . 997 30.7.2 LPTIM interrupt clear register (LPTIM_ICR) . . . . . . . . . . . . . . . . . . . . 999 30.7.3 LPTIM interrupt enable register (LPTIM_IER) . . . . . . . . . . . . . . . . . . 1000 30.7.4 LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . 1002 30.7.5 LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 1004 30.7.6 LPTIM compare register (LPTIM_CMP) . . . . . . . . . . . . . . . . . . . . . . 1006 30.7.7 LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . 1006 30.7.8 LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . 1007 30.7.9 LPTIM1 option register (LPTIM1_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1007 30.7.10 LPTIM2 option register (LPTIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1008 30.7.11 LPTIM configuration register 2 (LPTIM_CFGR2) . . . . . . . . . . . . . . . 1008 30.7.12 LPTIM repetition register (LPTIM_RCR) . . . . . . . . . . . . . . . . . . . . . . 1009 30.7.13 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 31 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012 32 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 32.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 32.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 32.3.1 IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 32.3.2 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014

RM0394 Contents 32.3.3 Hardware watchdog 1015 323.4 Low-power freeze 1015 32.3.5 Behavior in Stop and Standby modes 1015 3236 Register access protection 1015 32.3.7 Debug mode 1015 32.4 MWDG registers.......................................... 1016 32.4.1 Key register(IWDG KR)............................ 1016 3242 Prescaler register (IWDG PR) 1017 324.3 Reload register(IWDG_RLR) 1018 32.4.4 Status register (IWDG SR) 1019 3245 Window register (IWDG_WINR) 32.4.6 IWDG register map 33 System window watchdog(WWDG) 1022 33.1 Intro0 duction..................... 1022 33.2 WDG main features 1022 33.3 WDG functional description 1022 33.3.1 wDG block diagram....................... 102 33.3.2 Enabling the watchdog 1023 33.3.3 Controlling the downcounter 1023 33.3.4 Advanced watchdog interrupt feature 10e 33.3.5 How to program the watchdog timeout 1024 33.3.6 Debug mode 1025 33.4 WWDG registers 1026 334.1 Control register (WWDG_CR 1026 33.4.2 Configuration register (WDG CFR) 1026 33.4.3 Status register (WWDG SR) ,1027 33.4.4 WDG register map 1028 Real-time clock(RTC)applied to STM32L41xxx and STM32L42xxx devices only ................1029 34.1 Introduction 1029 34.2 RTC main features 1029 34.3 RTC functional description 1030 34.3.1 RTC block diagram 1030 34.3.2 RTC pins and internal signals............................ .1032 RM0394 Rev4 29/1600

RM0394 Rev 4 29/1600 RM0394 Contents 43 32.3.3 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 32.3.4 Low-power freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 32.3.5 Behavior in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . 1015 32.3.6 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 32.3.7 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 32.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 32.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 32.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 32.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 32.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019 32.4.5 Window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020 32.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 33 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . 1022 33.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 33.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 33.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 33.3.1 WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 33.3.2 Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 33.3.3 Controlling the downcounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 33.3.4 Advanced watchdog interrupt feature . . . . . . . . . . . . . . . . . . . . . . . . 1023 33.3.5 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . 1024 33.3.6 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 33.4 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026 33.4.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026 33.4.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . 1026 33.4.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027 33.4.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 34 Real-time clock (RTC) applied to STM32L41xxx and STM32L42xxx devices only . . . . . . . . . . . . . . . . 1029 34.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029 34.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029 34.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030 34.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030 34.3.2 RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032

Contents RM0394 3433 GPIOs controlled by the RTC and TAMP 44 1033 34.3.4 Clock and prescalers.....................................1035 3435 Real-time clock and calendar .1036 34.3.6 Calendar ultra-low power mode 1036 34.3.7 Pr0 grammable alarms,.,,.,,。,..,。,,。,,.,,.,,。,,.,.,, 1036 34.3.8 Periodic auto-wakeup 1037 343.9 RTC initialization and configuration 1038 34.3.10 Reading the calendar 1040 34.3.11 Resetting the RTC 1041 34.3.12 RTC synchronization.................................... 1047 34.3.13 RTC reference clock detection 1041 34.3.14 RTC smooth digital c calibration 1042 34.3.15 Timestamp function 1044 34 3 16 Calibration clock outout 1045 34.3.17 Tamper and alarm outpu 。。。 1046 344 RTC low-power modes. 1046 34.5 RTC interrupts 1047 34.6 RTC registers............... 104 34.6.1 RTC time register(RTC TR) 1047 34.62 RTC date register(RTC_DR) 1049 34.6.3 RTC sub second register (RTC SSR)..................... 1050 3464 RTC initialization control and status register(RTC ICSR) 1050 34.6.5 RTC prescaler register(RTC_PRER) 1052 34.6.6 RTC wakeup timer register(RTC WUTR) 1052 34.6.7 RTC control register(RTC_CR) 1053 34.68 RTC write protection register(RTC WPR) 1056 346.9 RTC calibration register(RTC CALR). 1057 34.6.10 RTC shift control register(RTC_SHIFTR) 1058 34.6.11 RTC timestamp time register(RTC TSTR) 1059 34.6.12 RTC timestamp date register(RTC_TSDR) 1059 34.613 RTC timestamp sub second register(RTC_TSSSR) 1060 346.14 RTC alarm A reaister (RTC ALRMAR) 1060 34.6.15 RTC alarm A sub second register(RTC_ALRMASSR) 1061 34.6.16 RTC alarm B register(RTC ALRMBR)... 1062 34.6.17 RTC alarm B sub second register(RTC ALRMBSSR) 1063 34.6.18 RTC status register(RTC_SR) 1064 34.6.19 RTC masked interrupt status register(RTC MISR) 1065 30/1600 RM0394 Rev 4 7

Contents RM0394 30/1600 RM0394 Rev 4 34.3.3 GPIOs controlled by the RTC and TAMP . . . . . . . . . . . . . . . . . . . . . . 1033 34.3.4 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035 34.3.5 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 34.3.6 Calendar ultra-low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 34.3.7 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 34.3.8 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037 34.3.9 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 1038 34.3.10 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 34.3.11 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 34.3.12 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 34.3.13 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 34.3.14 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042 34.3.15 Timestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044 34.3.16 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045 34.3.17 Tamper and alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 34.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 34.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 34.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 34.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 34.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049 34.6.3 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 1050 34.6.4 RTC initialization control and status register (RTC_ICSR) . . . . . . . . 1050 34.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 1052 34.6.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 1052 34.6.7 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053 34.6.8 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 1056 34.6.9 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 1057 34.6.10 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 1058 34.6.11 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 1059 34.6.12 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . 1059 34.6.13 RTC timestamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 1060 34.6.14 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 1060 34.6.15 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . 1061 34.6.16 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . 1062 34.6.17 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . 1063 34.6.18 RTC status register (RTC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064 34.6.19 RTC masked interrupt status register (RTC_MISR) . . . . . . . . . . . . . 1065