RM0394 Contents 34.6.20 RTC status clear register(RTC_SCR) .1066 34.6.21 RTC register map.................................... 1067 Tamper and backup registers (TAMP)........................1069 35.1 Introduction 1069 35.2 TAMP main features 1069 35.3 TAMP functional description 1070 35.3.1 TAMP block diagram 1070 35.3.2 TAMP pins and internal signals 1070 35.3.3 Tamper detection 1071 35.4 TAMP low-power modes 。。。。。。。。。,。。。,。。。。。。,。。 1073 35.5 TAMP interrupts 1073 35.6 TAMP registers... 1074 35.61 TAMP control register 1(TAMP CR1) 1074 35.6.2 TAMP control register 2(TAMP_CR2) 1075 35.6.3 TAMP filter control register (TAMP_FLTCR) 35.6.4 TAMP interrupt enable register(TAMP_IER)................ 1077 35.6.5 TAMP status register (TAMP SR) 1078 356.6 TAMP masked interrupt status register (TAMP_MISR) 1079 35.6.7 TAMP status clear register (TAMP SCR)............ 1079 35.6.8 TAMP backup x register (TAMP BKPXR) 1080 35.6.9 TAMP register map 108 36 Real-time clock(RTC)applied to sTM32L43x/44x/45x/46 x devices only............1082 36.1 Introduction 。 1082 36.2 RTC main features 1083 36.3 RTC functional description 1084 36.3.1 RTC block diagram 1084 36.3.2 GPlOs controlled by the RTC........................... 1085 36.3.3 Clock and prescalers 1087 36.3.4 Real-time clock and calenda 108e 36.3.5 Programmable alarms 1088 36.3.6 Periodic auto-wakeup 1088 36.3.7 RTC initialization and configuration 1089 36.3.8 Reading the calendar........ 1091 7 RM0394 Rev4 31/1600
RM0394 Rev 4 31/1600 RM0394 Contents 43 34.6.20 RTC status clear register (RTC_SCR) . . . . . . . . . . . . . . . . . . . . . . . . 1066 34.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067 35 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . 1069 35.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 35.2 TAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 35.3 TAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 35.3.1 TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 35.3.2 TAMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 35.3.3 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071 35.4 TAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 35.5 TAMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 35.6 TAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 35.6.1 TAMP control register 1 (TAMP_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 1074 35.6.2 TAMP control register 2 (TAMP_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 1075 35.6.3 TAMP filter control register (TAMP_FLTCR) . . . . . . . . . . . . . . . . . . . 1076 35.6.4 TAMP interrupt enable register (TAMP_IER) . . . . . . . . . . . . . . . . . . . 1077 35.6.5 TAMP status register (TAMP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 35.6.6 TAMP masked interrupt status register (TAMP_MISR) . . . . . . . . . . . 1079 35.6.7 TAMP status clear register (TAMP_SCR) . . . . . . . . . . . . . . . . . . . . . 1079 35.6.8 TAMP backup x register (TAMP_BKPxR) . . . . . . . . . . . . . . . . . . . . . 1080 35.6.9 TAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 36 Real-time clock (RTC) applied to STM32L43x/44x/45x/46x devices only . . . . . . . . . . . . . . . . . . . . . . . . 1082 36.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082 36.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 36.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 36.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 36.3.2 GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 36.3.3 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087 36.3.4 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088 36.3.5 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088 36.3.6 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088 36.3.7 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 36.3.8 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
Contents RM0394 3639 Resetting the RTC 4 1092 36.3.10 RTC synchronization.....................................1092 36.3.11 RTC reference clock detection .1093 36.3.12 RTC smooth digital calibration 1094 36.3.13Time-stamp function,,,..,.....,..,,.,..,.,,.,..,..,, 1096 36.3.14 Tamper detection 1096 36.3.15 Calibration clock outpu 36.3.16 Alarm output...... .1099 36.4 RTC low-power modes 109g 36.5 RTC interrupts 1100 36.6 RTC reaisters .1101 36.6.1 RTC time register(RTC_TR) 1101 36.6.2 RTC date register(RTC DR).................,......... .1102 2663 RTC control register (RTC CR) 1103 36.6.4 RTC initialization and status register(RTC_ISR) 106 36.6.5 RTC prescaler register(RTC PRER)........ 1109 36.6.6 RTC wakeup timer register(RTC_WUTR) 1110 36.67 RTC alarm A register(RTC_ALRMAR) 11 36.6.8 RTC alarm B register(RTC ALRMBR) 1112 36.69 RTC write protection register (RTC_WPR 1113 36.6.10 RTC sub second register (RTC SSR)..................... .1113 36.6.11 RTC shift control register(RTC_SHIFTR) 1114 36.6.12 RTC timestamp time register(RTC_TSTR) 1115 366.13 RTC timestamp date reaister(RTC TSDR) 1116 36.6.14 RTC time-stamp sub second register(RTC_TSSSR) 1117 36.6.15 RTC calibration register(RTC_CALR) 1118 36.6.16 RTC tamper configuration register(RTC TAMPCR) 1119 36.6.17 RTC alarm A sub second register(RTC_ALRMASSR) 122 36.6.18 RTC alarm B sub second register(RTC ALRMBSSR)..... ,.1123 36.6.19 RTC option register(RTC_OR)... .1124 36.6.20 RTC backup registers (RTC_BKPXR) .1124 36.6.21 RTC register map 。。。。。，。 .1125 31 Inter-integrated circuit(12C)interface 1127 37.1 Introduction .1127 37.2 2 C main features...............1127 32/1600 RM0394 Rev4 7
Contents RM0394 32/1600 RM0394 Rev 4 36.3.9 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092 36.3.10 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092 36.3.11 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093 36.3.12 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094 36.3.13 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096 36.3.14 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096 36.3.15 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098 36.3.16 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099 36.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099 36.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1100 36.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1101 36.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101 36.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102 36.6.3 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103 36.6.4 RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . 1106 36.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 1109 36.6.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 1110 36.6.7 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 1111 36.6.8 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . 1112 36.6.9 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 1113 36.6.10 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 1113 36.6.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 1114 36.6.12 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 1115 36.6.13 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . 1116 36.6.14 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . 1117 36.6.15 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 1118 36.6.16 RTC tamper configuration register (RTC_TAMPCR) . . . . . . . . . . . . . 1119 36.6.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . 1122 36.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . 1123 36.6.19 RTC option register (RTC_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124 36.6.20 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . 1124 36.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125 37 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . 1127 37.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1127 37.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1127
RM0394 Contents 37.3 12C implementation 1128 37.4 12C functional description .....1128 37.4.1 12C block diagram 1129 37.4.2 12C clock requirements 3743 Mode selection 1130 374.4 12C initializatior 13 37.4.5 Software reset 1135 37.4.6 Data transfer 1136 374.7 .1138 3748 12C master mode 1147 374.9 2C_TIMINGR register configuration examples 1159 37.4.10 SMBus specific features 1160 37 4.11 SMBus initialization 116 37.4.12 SMBus:I2C_TIMEOUTR register configuration examples .1165 374.13 SMBus slave mode 1165 37.4.14 Wakeup from Stop mode on address match 1173 37.4.15 Error conditions 37.4.16 DMA requests ,1175 37.4.17 Debug mode 176 37.5 12C low-power modes .1176 37.6 l2 C interrupts.................1177 37.7 12C registers 1177 37.7.1 12C control register 1 (12C CR1)......................... .1177 37.7.2 12C control register 2(12C_CR2) 1180 37.7.3 12C own address 1 register(12C_OAR1) 118e 3774 12C own address 2 register(12C OAR2) 1184 37.7.5 12C timing register(12C_TIMINGR) 1185 37.7.6 12C timeout register(12C_TIMEOUTR) 1186 3777 12C interrupt and status register (12C ISR) 1187 37.7.8 12C interrupt clear register (12C_ICR)( 1189 37.7.9 2 C PEC reaister2 C PECR)..,........,..,.,,......., ,1190 37.7.10 12C receive data register(12C_RXDR) 1191 37.7.11 12C transmit data register(12C_TXDR) 19 37.7.12 12C register map 1192 1194 RM0394 Rev 33/1600
RM0394 Rev 4 33/1600 RM0394 Contents 43 37.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1128 37.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1128 37.4.1 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129 37.4.2 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130 37.4.3 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130 37.4.4 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131 37.4.5 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135 37.4.6 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136 37.4.7 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138 37.4.8 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 37.4.9 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 1159 37.4.10 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160 37.4.11 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163 37.4.12 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . 1165 37.4.13 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165 37.4.14 Wakeup from Stop mode on address match . . . . . . . . . . . . . . . . . . . 1173 37.4.15 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173 37.4.16 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175 37.4.17 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176 37.5 I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1176 37.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1177 37.7 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1177 37.7.1 I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177 37.7.2 I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180 37.7.3 I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . 1183 37.7.4 I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . 1184 37.7.5 I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1185 37.7.6 I2C timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . 1186 37.7.7 I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . 1187 37.7.8 I2C interrupt clear register (I2C_ICR)( . . . . . . . . . . . . . . . . . . . . . . . . 1189 37.7.9 I2C PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190 37.7.10 I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . 1191 37.7.11 I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . 1191 37.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 38 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmitter (UART) . . . . . . . . . . 1194
Contents RM0394 38.1 Introduction 1194 38.2 USART main features .1194 38.3 USART extended features 1195 38.4 USART implementation 1196 38.5 USART functional description .1196 385.1 USART character description 199 38.5.2 USART transmitter 1201 38.5.3 USART receiver 1203 38.54 USART baud rate generation 1210 38.5.5 Tolerance of the USART receiver to clock deviation ,1212 38.56 USART auto baud rate detection 1213 38.5.7 Multiprocessor communication using USART ........... 1214 3858 Modbus communication using USART 1216 38.5.9 USART parity control 1217 38.5.10 USART LIN (local interconnection network)mode .1218 38.5.11 USART synchronous mode 1220 38.512 USART Single-wire Half-duplex communication 1223 385 13 USART Smartcard mode 1223 38.5.14 USART IrDA SIR ENDEC block 1228 38.5.15 USART continuous communication in DMA mode 1230 38.5.16 RS232 hardware flow control and Rs485 driver enable using USART...... 1232 38.5.17 Wakeup from Stop mode using USART ,1234 38.6 USART low-power modes 。。。。。。。。。。。。。。。。 。。。。。。 1236 38.7 USART interrupts 1236 38.8 USART registers 1238 388.1 Control register 1(USART_CR1). 123 38.8.2 Control register 2(USART CR2) 1241 38.8.3 Control register 3(USART_CR3) 1245 38.8.4 Baud rate register(USART BRR) 1249 3885 Guard time and prescaler register(USART GTPR) 1249 38.86 Receiver timeout register (USARTRTOR) 1251 38.8.7 Request register (USART ROR)...... 1252 38.8.8 nterrupt and status register (USART_ISR) 1253 38.8.9 Interrupt flag clear register(USART_ICR) 1257 38.8.10 Receive data register(USART_RDR) .1259 34/1600 RM0394 Rev 4 7
Contents RM0394 34/1600 RM0394 Rev 4 38.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1194 38.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1194 38.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1195 38.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1196 38.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1196 38.5.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199 38.5.2 USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201 38.5.3 USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203 38.5.4 USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210 38.5.5 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . 1212 38.5.6 USART auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213 38.5.7 Multiprocessor communication using USART . . . . . . . . . . . . . . . . . . 1214 38.5.8 Modbus communication using USART . . . . . . . . . . . . . . . . . . . . . . . 1216 38.5.9 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217 38.5.10 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . 1218 38.5.11 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220 38.5.12 USART Single-wire Half-duplex communication . . . . . . . . . . . . . . . . 1223 38.5.13 USART Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223 38.5.14 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228 38.5.15 USART continuous communication in DMA mode . . . . . . . . . . . . . . 1230 38.5.16 RS232 hardware flow control and RS485 driver enable using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232 38.5.17 Wakeup from Stop mode using USART . . . . . . . . . . . . . . . . . . . . . . . 1234 38.6 USART low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 38.7 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 38.8 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238 38.8.1 Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238 38.8.2 Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241 38.8.3 Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245 38.8.4 Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249 38.8.5 Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . 1249 38.8.6 Receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . . . . . . . 1251 38.8.7 Request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252 38.8.8 Interrupt and status register (USART_ISR) . . . . . . . . . . . . . . . . . . . . 1253 38.8.9 Interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . . . . . . . . 1257 38.8.10 Receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . . . . . . . 1259
RM0394 Contents 38.8.11 Transmit data register(USART_TDR) .1259 38.8.12 USART register map 1260 Low-power universal asynchronous receiver transmitter (LPUART).....................................1262 39.1 Introduction 1262 39.2 LPUART main features 1263 39.3 LPUART implementation 1263 39.4 LPUART functional description 1264 39.4.1 LPUART character description 1266 39.4.2 LPUART transmitter 1268 39.4.3 LPUART receiver 1270 39.4.4 LPUART baud rate generation 1273 394.5 Tolerance of the LPUART receiver to clock deviation 127 39.4.6 Multiprocessor communication using LPUART .. 1276 39.4.7 LPUART parity control. 1278 394.8 Single-wire Half-duplex communication using LPUART .........1279 39.4.9 Continuous communication in DMA mode using LPUART ...1279 39 4.10 RS232 1282 39.4.11 Wakeup from Stop mode using LPUART 128 39.5 LPUART low-power mode 1286 39.6 LPUART interrupts....................................... 1287 39.7 LPUART registers 1289 39.7.1 Control register 1(LPUART_CR1). 1289 3972 Control register 2(LPUART_CR2) 1291 39.7.3 Control register 3(LPUART_CR3) 。。。。。。，。。。。。 39.7.4 Baud rate register(LPUART_BRR) 1296 39.75 Request register(LPUART_RQR) 1296 39.7.6 Interrupt status register(LPUART ISR). 。。。。。。。。。。。 1297 39.7.7 interrupt flag clear register (LPUART_ICR) 1300 39.7.8 Receive data register(LPUART_RDR) 1301 39.7.9 Transmit data register(LPUART_TDR) 1301 39.7.10 LPUART register map......... ,1303 Serial peripheral interface (SPI).............................1304 40.1 Introduction 1304 RM0394 Rev 4 35/1600
RM0394 Rev 4 35/1600 RM0394 Contents 43 38.8.11 Transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . . . . . . . 1259 38.8.12 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260 39 Low-power universal asynchronous receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262 39.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262 39.2 LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263 39.3 LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263 39.4 LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264 39.4.1 LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266 39.4.2 LPUART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268 39.4.3 LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 39.4.4 LPUART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 39.4.5 Tolerance of the LPUART receiver to clock deviation . . . . . . . . . . . . 1275 39.4.6 Multiprocessor communication using LPUART . . . . . . . . . . . . . . . . . 1276 39.4.7 LPUART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278 39.4.8 Single-wire Half-duplex communication using LPUART . . . . . . . . . . 1279 39.4.9 Continuous communication in DMA mode using LPUART . . . . . . . . 1279 39.4.10 RS232 Hardware flow control and RS485 Driver Enable using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282 39.4.11 Wakeup from Stop mode using LPUART . . . . . . . . . . . . . . . . . . . . . . 1285 39.5 LPUART low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286 39.6 LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287 39.7 LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289 39.7.1 Control register 1 (LPUART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289 39.7.2 Control register 2 (LPUART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291 39.7.3 Control register 3 (LPUART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294 39.7.4 Baud rate register (LPUART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 39.7.5 Request register (LPUART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 39.7.6 Interrupt & status register (LPUART_ISR) . . . . . . . . . . . . . . . . . . . . . 1297 39.7.7 Interrupt flag clear register (LPUART_ICR) . . . . . . . . . . . . . . . . . . . . 1300 39.7.8 Receive data register (LPUART_RDR) . . . . . . . . . . . . . . . . . . . . . . . 1301 39.7.9 Transmit data register (LPUART_TDR) . . . . . . . . . . . . . . . . . . . . . . . 1301 39.7.10 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303 40 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304 40.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304