高职嵌入式教材配套电子资源（技术资料）STM32L4xx参考手册（RM0394 Reference manual）advanced Arm-based 32-bit MCUs

RM0394 Contents 25.3 AES implementation 666 25.4 AES functional description .6 25.4.1 AES block diagram 66 25.4.2 AES internal signals...................................... .666 2543 AES cryptographic core 667 25.4.4 AES procedure to perform a cipher operation 672 25.4.5 AES decryption key preparation 676 25.4.6 AES ciphertext stealing and data padding 677 254.7 AES task suspend and resume ......................... 6 25.4.8 AES basic chaining modes(ECB.CBC) 679 25.4.9 AES counter(CTR)mode 684 25.4.10 AES Galois/counter mode (GCM) 686 25.4.11 AES Galois message authentication code(GMAC) 691 25.412 AES counter with CBC-MAC(CCM).................... 693 25.4.13 .AES data registers and data swapping 698 25.4.14 AES key registers 700 25.4.15 AES initialization vector registers 700 25.4.16 AES DMA interface 700 25.4.17 AES error management 703 25.5 AES interrupts 703 25.6 AES processing latency..................................... 704 25.7 AES registers 705 25.7.1 AES control register(AES_CR).......................... .705 25.72 AES status register(AES_SR) 708 25.7.3 AES data input register(AES_DINR) 25.74 AES data output register(AES_DOUTR) .710 25.7.5 AES key register0(AES_KEYRO) 25.7.6 AES key register 1(AES KEYR1)... 711 2577 AES key register 2(AES KEYR2) 711 25.7.8 AES key register 3(AES_KEYR3) 712 25.79 AES initialization vector register 0(AES_IVRO) ,..712 25.7.10 AES initialization vector register 1(AES_IVR1) .712 25.711 AES initialization vector register 2(AES_IVR2) 25.7.12 AES initialization vector register 3(AES_IVR3) ,713 25.7.13 AES key register 4(AES_KEYR4) 714 25.7.14 AES key register5(AES KEYR5)............................714 RM0394 Rev4 21/1600

RM0394 Rev 4 21/1600 RM0394 Contents 43 25.3 AES implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 25.4 AES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 25.4.1 AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 25.4.2 AES internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 25.4.3 AES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 25.4.4 AES procedure to perform a cipher operation . . . . . . . . . . . . . . . . . . . 672 25.4.5 AES decryption key preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 25.4.6 AES ciphertext stealing and data padding . . . . . . . . . . . . . . . . . . . . . . 677 25.4.7 AES task suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 25.4.8 AES basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . . . . . . . 679 25.4.9 AES counter (CTR) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 25.4.10 AES Galois/counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 25.4.11 AES Galois message authentication code (GMAC) . . . . . . . . . . . . . . 691 25.4.12 AES counter with CBC-MAC (CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . 693 25.4.13 .AES data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . . . 698 25.4.14 AES key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 25.4.15 AES initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 25.4.16 AES DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 25.4.17 AES error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 25.5 AES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 25.6 AES processing latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 25.7 AES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 25.7.1 AES control register (AES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 25.7.2 AES status register (AES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 25.7.3 AES data input register (AES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . . 709 25.7.4 AES data output register (AES_DOUTR) . . . . . . . . . . . . . . . . . . . . . . 710 25.7.5 AES key register 0 (AES_KEYR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 25.7.6 AES key register 1 (AES_KEYR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 25.7.7 AES key register 2 (AES_KEYR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 25.7.8 AES key register 3 (AES_KEYR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 25.7.9 AES initialization vector register 0 (AES_IVR0) . . . . . . . . . . . . . . . . . . 712 25.7.10 AES initialization vector register 1 (AES_IVR1) . . . . . . . . . . . . . . . . . . 712 25.7.11 AES initialization vector register 2 (AES_IVR2) . . . . . . . . . . . . . . . . . . 713 25.7.12 AES initialization vector register 3 (AES_IVR3) . . . . . . . . . . . . . . . . . . 713 25.7.13 AES key register 4 (AES_KEYR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 25.7.14 AES key register 5 (AES_KEYR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

Contents RM0394 25.7.15 AES key register 6(AES_KEYR6) 714 25.7.16 AES key register7(AES KEYR70............................715 25.7.17 AES suspend registers(AES_SUSPxR).. ..715 25.7.18 AES register map 716 Advanced-control timers (TIM1) ..718 26.1 TIM1 introduction 718 26.2 TIM1 main features 719 26.3 TIM1 functional description .............................. 721 2631 Time-base unit 721 26.32 Counter modes 723 26.3.3 Repetition counter 734 26.34 Extemal trigger input 736 26.3.5 Clock selection....................................... 737 26.3.6 Capture/compare channels 741 26.37 Input capture mode 744 26.3.8 PWM input mode 745 26.3.9 Forced output mode 746 26.3.100 utput compare mode................................ 747 26.3.11 PWM mode 748 26.3,12 Asymmetric PWM mode 751 26.3.13 Combined PWM mode 752 26.3.14 Combined 3-phase PWM mode 753 26.315 Complementary outputs and dea d-time insertion 754 26.3.16 Using the break function ,756 26.3.17 Bidirectional break inputs 762 26.3.18 Clearing the OCxREF signal on an external event 763 26.3.19 6-step PWM generation 764 26.3.20 One-pulse mode 765 26.3.21 Retriggerable one pulse mode(OPM) .766 26.3.22 Encoder interface mode 767 26.3.23 76g 26.3.24 Timer input XOR function. 770 26.3.25 nterfacing with Hall sensor 770 26.3.26 Timer synchronization ,773 26.3.27 ADC synchronization 777 26 3.28 DMA burst mode 777 22/1600 RM0394 Rev 4 7

Contents RM0394 22/1600 RM0394 Rev 4 25.7.15 AES key register 6 (AES_KEYR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 25.7.16 AES key register 7 (AES_KEYR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 25.7.17 AES suspend registers (AES_SUSPxR) . . . . . . . . . . . . . . . . . . . . . . . 715 25.7.18 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 26 Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 26.1 TIM1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 26.2 TIM1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 26.3 TIM1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 26.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 26.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 26.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 26.3.4 External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 26.3.5 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 26.3.6 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 26.3.7 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 26.3.8 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 26.3.9 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 26.3.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 26.3.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 26.3.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 26.3.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 26.3.14 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 26.3.15 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 754 26.3.16 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 26.3.17 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 26.3.18 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 763 26.3.19 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 26.3.20 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 26.3.21 Retriggerable one pulse mode (OPM) . . . . . . . . . . . . . . . . . . . . . . . . . 766 26.3.22 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 26.3.23 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 26.3.24 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 26.3.25 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 26.3.26 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 26.3.27 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 26.3.28 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

RM0394 Contents 26.3.29 Debug mode 778 26.4 TIM1 registers... 779 26.4.1 TIM1 control register 1(TIM1_CR1) 779 264.2 TIM1 control register 2(TIM1_CR2) 26.43 TIM1 slave mode control register(TIM1_SMCR) 783 26.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER 785 26.4.5 TIM1 status register (TIM1 SR)......................... ....787 2646 TIM1 event generation register (TIM1 EGR) 789 264.7 TIM1 ompare mode register 1[alterate) .790 26.4.8 ompare mode register 1 [alternate) .791 264.9 794 2610mmod rseremate] 795 24.1mre ner 797 26.4.12TlM1 counter(TlM1CNT,,.,,.,..,..,.,,.,,.,.,,.,..,.,, ,800 26.4.13 TIM1 prescaler(TIM1_PSC) 800 26.414 TIM1 auto-reload register(TIM1_ARR) 800 26.4.15 TIM1 repetition counter register(TIM1_RCR) 801 26.4.16 TIM1 capture/compare register 1(TIM1_CCR1) 801 26.4.17 TIM1 capture/compare register 2(TIM1_CCR2)................ 802 26.4.18 TIM1 capture/compare register 3(TIM1 CCR3) 802 26.4.19 TIM1capture/compare register (TIM1_CCR4 803 264016ea4meos 803 26.4.21 TIM1 DMA control register (TIM1_DCR) .806 26.4.22 TIM1 DMA address for full transfer (TIM1 DMAR) 807 26.4.23 TIM1 option register 1(TIM1_OR1) 808 808 26.4.25 TIM1 capture/compare register 5(TIM1 CCR5)............. .809 26.4.26 TIM1 capture/compare register 6(TIM1_CCR6) 810 26.427 TIM1 option register 2(TIM1_OR2).. 81 26.4.28 TIM1 option register 3(TIM1_OR3) 812 26.4.29 TIM1 register map 814 7 RM0394 Rev4 23/1600

RM0394 Rev 4 23/1600 RM0394 Contents 43 26.3.29 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 26.4 TIM1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 26.4.1 TIM1 control register 1 (TIM1_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 779 26.4.2 TIM1 control register 2 (TIM1_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 780 26.4.3 TIM1 slave mode control register (TIM1_SMCR) . . . . . . . . . . . . . . . . 783 26.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . . . . . . . . . . . . 785 26.4.5 TIM1 status register (TIM1_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 26.4.6 TIM1 event generation register (TIM1_EGR) . . . . . . . . . . . . . . . . . . . 789 26.4.7 TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 26.4.8 TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 26.4.9 TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 26.4.10 TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 26.4.11 TIM1 capture/compare enable register (TIM1_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 26.4.12 TIM1 counter (TIM1_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 26.4.13 TIM1 prescaler (TIM1_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 26.4.14 TIM1 auto-reload register (TIM1_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 800 26.4.15 TIM1 repetition counter register (TIM1_RCR) . . . . . . . . . . . . . . . . . . . 801 26.4.16 TIM1 capture/compare register 1 (TIM1_CCR1) . . . . . . . . . . . . . . . . . 801 26.4.17 TIM1 capture/compare register 2 (TIM1_CCR2) . . . . . . . . . . . . . . . . . 802 26.4.18 TIM1 capture/compare register 3 (TIM1_CCR3) . . . . . . . . . . . . . . . . . 802 26.4.19 TIM1 capture/compare register 4 (TIM1_CCR4) . . . . . . . . . . . . . . . . . 803 26.4.20 TIM1 break and dead-time register (TIM1_BDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 26.4.21 TIM1 DMA control register (TIM1_DCR) . . . . . . . . . . . . . . . . . . . . . . . 806 26.4.22 TIM1 DMA address for full transfer (TIM1_DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 26.4.23 TIM1 option register 1 (TIM1_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 26.4.24 TIM1 capture/compare mode register 3 (TIM1_CCMR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 26.4.25 TIM1 capture/compare register 5 (TIM1_CCR5) . . . . . . . . . . . . . . . . . 809 26.4.26 TIM1 capture/compare register 6 (TIM1_CCR6) . . . . . . . . . . . . . . . . . 810 26.4.27 TIM1 option register 2 (TIM1_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 26.4.28 TIM1 option register 3 (TIM1_OR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 26.4.29 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

Contents RM0394 27 General-purpose timers(TIM2/TIM3) 817 27.1 TIM2/TIM3 introduction 817 27.2 TIM2/TIM3 main features... 817 27.3 TIM2/TIM3 functional descriptior 819 27.3.1 Time-base unit 819 27.3.2 Counter modes 821 27.3.3 Clock selection...,......··· 27.3.4 Capture/Compare channels 835 273.5 Input capture mode 837 27.3.6 PWM input mode 838 27.3.7 Forced output mode B39 273.8 Output compare mode................................... 27.3.9 PWM mode..... 27.3.10 Asymmetric PWM mode 844 27.3.11 Combined PWM mode 5 27.3.12 Clearing the OCxREF signal on an external event 846 273.13 One-pulse mode 848 27.3.14 Retriggerable one pulse mode(OPM) 849 27.3.15 Encoder interface mode 850 27.3.16 UIF bit remapping.. 27.3.17 Timer input XOR function. 852 27.3.18 Timers and external trigge synchronization 853 27.3.19 Timer synchronization................,............. 856 27.3.20 DMA burst mode 860 27.3.21 Debug mode 861 27.4 TIM2/TIM3 registers... 862 27.4.1 TIMx control register 1(TIMx_CR1)(x=2 to 3) 662 27.4.2 TIMx control register 2(TIMx CR2)(x=2 to 3) 863 27.4.3 TIMx slave mode control register(TIMx_SMCR)(x=2 to 3) 865 27.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)(x=2 to 3). 2745 TIMx status register (TIMx SR)(x 2 to 3) 869 274.6 TIMx event generation register (TIMx_EGR)(x=2to 3) 870 27.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)(x=2 to 3). .871 27.4.8 27.4.9 ure/compare mode register 2(TIMx_CCMR2 TIMx capture/compare enable register (TIMx_CCER)(x=2to 3) 27.4.10 TIMx counter (TIMx_CNT)(x=2 to 3). ..878 24/1600 RM0394 Rev4 7

Contents RM0394 24/1600 RM0394 Rev 4 27 General-purpose timers (TIM2/TIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . 817 27.1 TIM2/TIM3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 27.2 TIM2/TIM3 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 27.3 TIM2/TIM3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 27.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 27.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 27.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 27.3.4 Capture/Compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 27.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 27.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 27.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 27.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 27.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 27.3.10 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 27.3.11 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 27.3.12 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 846 27.3.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 27.3.14 Retriggerable one pulse mode (OPM) . . . . . . . . . . . . . . . . . . . . . . . . . 849 27.3.15 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 27.3.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 27.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 27.3.18 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 853 27.3.19 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856 27.3.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 27.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 27.4 TIM2/TIM3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 27.4.1 TIMx control register 1 (TIMx_CR1)(x = 2 to 3) . . . . . . . . . . . . . . . . . . 862 27.4.2 TIMx control register 2 (TIMx_CR2)(x = 2 to 3) . . . . . . . . . . . . . . . . . . 863 27.4.3 TIMx slave mode control register (TIMx_SMCR)(x = 2 to 3) . . . . . . . . 865 27.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 3) . . . . . . . 868 27.4.5 TIMx status register (TIMx_SR)(x = 2 to 3) . . . . . . . . . . . . . . . . . . . . . 869 27.4.6 TIMx event generation register (TIMx_EGR)(x = 2 to 3) . . . . . . . . . . . 870 27.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 3) . . 871 27.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 3) . . 875 27.4.9 TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 3) . . . . 877 27.4.10 TIMx counter (TIMx_CNT)(x = 2 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . 878

RM0394 Contents 27.4.11 TIMx prescaler (TIMx_PSC)(x=2 to 3) 879 27.4.12 TIMx auto-reload register (TIMx_ARR)(x=2 to 3) 87g 27.4.13 TIMx capture/compare register 1(TIMx_CCR1)(x=2 to 3) 880 27.4.14 TIMx capture/compare register 2(TIMx_CCR2)(x=2to 3) 880 27.4.15 TIMx capture/compare register 3(TIMx CCR3)(x 2 to 3) 881 27.4.16 TIMx capture/compare register 4 (TIMx CCR4)(x =2 to 3) 881 27.4.17 TIMx DMA control register (TIMx_DCR)(x=2to 3).... 882 27.4.18 TIMx DMA address for ful transfer (TIMx_DMAR)(x=2 to 3)....... 882 27.4.19 TIM2 option register 1 (TIM2_OR1)................ 883 27.4.20 TIM2 option register 2(TIM2_OR2) 27.4.21 TIMx register map............ 884 28 General-purpose timers (TIM15/TIM16)........................ 887 28.1 TIM15/TIM16 introduction 887 28.2 TIM15 main features 887 28.3 TIM16 main features 888 28.4 Implementation. 890 28.5 TIM15/TIM16 functional description............................891 28.5.1 Time-base unit 891 28.5.2 Counter modes 89 28.5.3 Repetition counter 897 28.5.4 Clock selection. 898 28.5.5 Capture/compare channels 900 2856 Input capture mode 902 28.57 PWM input mode (only for TIM15) 903 28.5.8 Forced output mode. 904 28.5.9 Output compare mode 905 28.5.10 PWM mode 6 28.5.11 Combined PWM mode (TIM15 onty) 28.5.12 Complementary outputs and dead-time insertior 908 28.5.13 Using the break function 910 28.5.14 One-pulse mode ,915 28.5.15 Retriggerable one pulse mode(OPM)(TIM15 only) 28.5.16 UIF bit remapping..... 917 28.5.17 Timer input XOR function (TIM15 only) 918 28.5.18 Extemal trigger synchronization(TIM15only) 91 28.5.19 Slave mode-combined reset trigger mode ,921 7 RM0394 Rev 4 25/1600

RM0394 Rev 4 25/1600 RM0394 Contents 43 27.4.11 TIMx prescaler (TIMx_PSC)(x = 2 to 3) . . . . . . . . . . . . . . . . . . . . . . . . 879 27.4.12 TIMx auto-reload register (TIMx_ARR)(x = 2 to 3) . . . . . . . . . . . . . . . 879 27.4.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 3) . . . . . . . . 880 27.4.14 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 3) . . . . . . . . 880 27.4.15 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 3) . . . . . . . . 881 27.4.16 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 3) . . . . . . . . 881 27.4.17 TIMx DMA control register (TIMx_DCR)(x = 2 to 3) . . . . . . . . . . . . . . . 882 27.4.18 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 3) . . . . . . . 882 27.4.19 TIM2 option register 1 (TIM2_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 27.4.20 TIM2 option register 2 (TIM2_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 27.4.21 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884 28 General-purpose timers (TIM15/TIM16) . . . . . . . . . . . . . . . . . . . . . . . . 887 28.1 TIM15/TIM16 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 28.2 TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 28.3 TIM16 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888 28.4 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890 28.5 TIM15/TIM16 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891 28.5.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891 28.5.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 28.5.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897 28.5.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898 28.5.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 28.5.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902 28.5.7 PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903 28.5.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 28.5.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 28.5.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 28.5.11 Combined PWM mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . . 907 28.5.12 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 908 28.5.13 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 28.5.14 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 28.5.15 Retriggerable one pulse mode (OPM) (TIM15 only) . . . . . . . . . . . . . . 916 28.5.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917 28.5.17 Timer input XOR function (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . 918 28.5.18 External trigger synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . . 919 28.5.19 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . . 921