高职嵌入式教材配套电子资源（技术资料）STM32L4xx参考手册（RM0394 Reference manual）advanced Arm-based 32-bit MCUs

RM0394 Contents 13.5.1 Interrupt mask register 1(EXTI_IMR1) 330 13.52 Event mask register 1(EXTI_EMR1) 30 13.5.3 Rising trigger selection register 1(EXTI_RTSR1) .331 1354 Falling trigger selection register1(EXTI_FTSR1) 331 135.5 Software interrupt event register 1 (EXTI SWIER1) 332 13.5.6 Pending register 1(EXTI PR1) 333 13.5.7 Interrupt mask register 2(EXTI_IMR2) 333 13.5.8 Event mask register 2 (EXTI EMR2) 334 13.5.9 Rising trigger selection register 2(EXTIRTSR2) 334 13.5.10 Falling trigger selection register2(EXTL_FTSR2) 13.5.11 Software interrupt event register 2(EXTI SWIER2) 335 13.5.12 Pending register2(EXTI_PR2) 336 13.5.13 EXTI register map................................., ,337 Cyclic redundancy check calculation unit(CRC) 338 14.1 Introduction 338 14.2 CRC main features 338 14.3 CRC functional description 339 14.3.1 CRC block diagram 14.3.2 CRC internal signals 339 14.3.3 CRC operation 339 14.4 CRC registers. 341 14.4.1 Data register(CRC_DR) 341 14.4.2 Independent data register(CRC IDR) 341 14.4.3 Control register(CRC_CR) 342 144.4 Initial CRC value(CRC_INIT) 342 14.4.5 CRC polynomial (CRC POL) 343 14.4.6 CRC register map 343 15 Quad-SPI interface (QUADSPI)..............................344 15.1 Introduction 344 15.2 QUADSPI main features 344 15.3 QUADSPI functional description 344 15.3.1 QUADSPI block diagram 344 15.3.2 ................. 345 15.3.3 QUADSPI command sequence 346 7 RM0394 Rev4 1W1600

RM0394 Rev 4 11/1600 RM0394 Contents 43 13.5.1 Interrupt mask register 1 (EXTI_IMR1) . . . . . . . . . . . . . . . . . . . . . . . . 330 13.5.2 Event mask register 1 (EXTI_EMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 330 13.5.3 Rising trigger selection register 1 (EXTI_RTSR1) . . . . . . . . . . . . . . . . 331 13.5.4 Falling trigger selection register 1 (EXTI_FTSR1) . . . . . . . . . . . . . . . . 331 13.5.5 Software interrupt event register 1 (EXTI_SWIER1) . . . . . . . . . . . . . . 332 13.5.6 Pending register 1 (EXTI_PR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 13.5.7 Interrupt mask register 2 (EXTI_IMR2) . . . . . . . . . . . . . . . . . . . . . . . . 333 13.5.8 Event mask register 2 (EXTI_EMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 334 13.5.9 Rising trigger selection register 2 (EXTI_RTSR2) . . . . . . . . . . . . . . . . 334 13.5.10 Falling trigger selection register 2 (EXTI_FTSR2) . . . . . . . . . . . . . . . . 335 13.5.11 Software interrupt event register 2 (EXTI_SWIER2) . . . . . . . . . . . . . . 335 13.5.12 Pending register 2 (EXTI_PR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 13.5.13 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 338 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 14.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 14.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 14.3.1 CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 14.3.2 CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 14.3.3 CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 14.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 14.4.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 14.4.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . 341 14.4.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 14.4.4 Initial CRC value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 14.4.5 CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 14.4.6 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 15 Quad-SPI interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 15.2 QUADSPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 15.3 QUADSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 15.3.1 QUADSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 15.3.2 QUADSPI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 15.3.3 QUADSPI command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

Contents RM0394 1534 QUADSPI signal interface protocol modes 348 15.3.5 QUADSPI indirect mode...................................350 1536 QUADSPI status flag polling mode .352 15.3.7 QUADSPI memory-mapped mode 352 15.3.8 QUADSPI Flash memory configuration....................... .353 15.3.9 QUADSPI delayed data sampling 353 153.10 QUADSPI configuration 15.3.11 QUADSPI usage 354 15.3.12 Sending the instruction only once 15.3.13 QUADSPI error management............................. .356 15.3.14 QUADSPI busy bit and abort functionality 357 15.3.15 nCS behavior 357 15.4 QUADSPI interrupts... 359 15.5 QUADSPI registers..................................... 360 15.5.1 QUADSPI control register(QUADSPI_CR) 360 15.5.2 QUADSPI device configuration register (QUADSPI_DCR) 363 15.5.3 QUADSPI status register(QUADSPI_SR) 364 15.5.4 QUADSPI flag clear register(QUADSPI_FCR) 365 15.5.5 QUADSPI data length register(QUADSPI DLR)......... 365 1556 QUADSPI communication configuration register (QUADSPI CCR) ,366 15.57 QUADSPI address register(QUADSPI_AR) 368 15.5.8 QUADSPI alternate bytes registers (QUADSPI ABR) 369 15.5.9 QUADSPI data register(QUADSPI_DR). 369 15.5.10 QUADSPIpolling status mask register (QUADSPIPSMKR). o 15.5.11 QUADSPI polling status match register(QUADSPI PSMAR) ,370 15.5.12 QUADSPI polling interval register(QUADSPI_PIR) 371 15.5.13 QUADSPI low-power timeout register (QUADSPI LPTR)......... ,371 15.5.14 QUADSPI register map ,372 16 Analog-to-digital conv erters(ADC) 。。。。·。。。”。。。”。。。。。 373 16.1 Introduction 373 16.2 ADC main features 374 163 ADC implementation................................... 375 16.4 ADC functional description 376 164.1 ADC block diagram 376 16.4.2 ADC pins and internal signals ..377 12/1600 RM0394 Rev4 7

Contents RM0394 12/1600 RM0394 Rev 4 15.3.4 QUADSPI signal interface protocol modes . . . . . . . . . . . . . . . . . . . . . 348 15.3.5 QUADSPI indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 15.3.6 QUADSPI status flag polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 15.3.7 QUADSPI memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 15.3.8 QUADSPI Flash memory configuration . . . . . . . . . . . . . . . . . . . . . . . . 353 15.3.9 QUADSPI delayed data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 15.3.10 QUADSPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 15.3.11 QUADSPI usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 15.3.12 Sending the instruction only once . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 15.3.13 QUADSPI error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 15.3.14 QUADSPI busy bit and abort functionality . . . . . . . . . . . . . . . . . . . . . . 357 15.3.15 nCS behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 15.4 QUADSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 15.5 QUADSPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 15.5.1 QUADSPI control register (QUADSPI_CR) . . . . . . . . . . . . . . . . . . . . . 360 15.5.2 QUADSPI device configuration register (QUADSPI_DCR) . . . . . . . . . 363 15.5.3 QUADSPI status register (QUADSPI_SR) . . . . . . . . . . . . . . . . . . . . . 364 15.5.4 QUADSPI flag clear register (QUADSPI_FCR) . . . . . . . . . . . . . . . . . . 365 15.5.5 QUADSPI data length register (QUADSPI_DLR) . . . . . . . . . . . . . . . . 365 15.5.6 QUADSPI communication configuration register (QUADSPI_CCR) . . 366 15.5.7 QUADSPI address register (QUADSPI_AR) . . . . . . . . . . . . . . . . . . . . 368 15.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) . . . . . . . . . . . . 369 15.5.9 QUADSPI data register (QUADSPI_DR) . . . . . . . . . . . . . . . . . . . . . . . 369 15.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR) . . . . . . . 370 15.5.11 QUADSPI polling status match register (QUADSPI _PSMAR) . . . . . . 370 15.5.12 QUADSPI polling interval register (QUADSPI _PIR) . . . . . . . . . . . . . . 371 15.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . . . . . . . 371 15.5.14 QUADSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 16 Analog-to-digital converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 16.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 16.3 ADC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 16.4 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 16.4.1 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 16.4.2 ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

RM0394 Contents 16.4.3 Clocks .378 164.4 ADC1/2 connectivity 380 16.4.5 Slave AHB interface ..382 16.4.6 ower-down mode(DEEPPWD)and ADC voltage regulator (ADVREGEN 382 16.4.7 Single-ended and differential input channels 383 16.4.8 Calibration (ADCAL.ADCALDIF.ADC CALFACT.... 383 16.49 ADC on-off control (ADEN.ADDIS.ADRDY) 386 16.4.10 Constraints when writing the ADC control bits 387 16.4.11 Channel selection (SQRx.JSORx) 388 16.4.12 Channel-wise programmable sampling time(SMPR1.SMPR2) 389 16.4.13 Single conversion mode (CONT=0)....................... 389 16.4.14 Continuous conversion mode (CONT=1). 390 16.4.15 Starting conversions(ADSTART,JADSTART) 391 16.4.16 ADC timing..................... 392 16.4.17 Stopping an ongoing conversion(ADSTP.JADSTP) 392 16.4.18 394 16.4.19 Injected channel management 16.4.20 Discontinuous mode (DISCEN,DISCNUM,JDISCEN) 398 16.4.21 Queue of context for injected conversions 399 16.4.22 Programmable resolution(RES)-fast conversion mode 407 16.4.23 End of conversion,end of sampling phase(EOC.JEOC.EOSMP) 408 16.424 End of conversion sequence(EOS.JEOS).......... 16.4.25 Timing diagrams example(single/continuous modes. hardware/software triggers)................................ 0g 164 26 Data management 411 16.4.27 Managing conversions using the DFSDM 416 16.4.28 Dynamic low-power features........... 417 16.4.29 Analog window watchdog(AWD1EN,JAWD1EN,AWD1SGL AWD1CH,AWD2CH.AWD3CH,AWD_HTx.AWD_LTx.AWDx)....422 16.4.30 Oversampler 426 16.4.31 Dual ADC modes 164.32 Temperature sensor 445 16.4.33 VBAT supply monitoring 447 16.4.34 Monitoring the intemal voltage reference 448 16.5 ADC interrupts 450 16.6 ADC registers(for each ADC) 451 7 RM0394 Rev4 13/1600

RM0394 Rev 4 13/1600 RM0394 Contents 43 16.4.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 16.4.4 ADC1/2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 16.4.5 Slave AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 16.4.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 16.4.7 Single-ended and differential input channels . . . . . . . . . . . . . . . . . . . . 383 16.4.8 Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . . . . . . . . . . . . 383 16.4.9 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . 386 16.4.10 Constraints when writing the ADC control bits . . . . . . . . . . . . . . . . . . . 387 16.4.11 Channel selection (SQRx, JSQRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 16.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . . 389 16.4.13 Single conversion mode (CONT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 16.4.14 Continuous conversion mode (CONT=1) . . . . . . . . . . . . . . . . . . . . . . . 390 16.4.15 Starting conversions (ADSTART, JADSTART) . . . . . . . . . . . . . . . . . . . 391 16.4.16 ADC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 16.4.17 Stopping an ongoing conversion (ADSTP, JADSTP) . . . . . . . . . . . . . . 392 16.4.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,JEXTSEL, JEXTEN) . . . . . . . . . . . . . . . . . . . . . . . 394 16.4.19 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 16.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . . . . . . . . . 398 16.4.21 Queue of context for injected conversions . . . . . . . . . . . . . . . . . . . . . . 399 16.4.22 Programmable resolution (RES) - fast conversion mode . . . . . . . . . . 407 16.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . 408 16.4.24 End of conversion sequence (EOS, JEOS) . . . . . . . . . . . . . . . . . . . . . 408 16.4.25 Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 16.4.26 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 16.4.27 Managing conversions using the DFSDM . . . . . . . . . . . . . . . . . . . . . . 416 16.4.28 Dynamic low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 16.4.29 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . 422 16.4.30 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 16.4.31 Dual ADC modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 16.4.32 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 16.4.33 VBAT supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 16.4.34 Monitoring the internal voltage reference . . . . . . . . . . . . . . . . . . . . . . 448 16.5 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 16.6 ADC registers (for each ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

Contents RM0394 1661 ADC intermrupt and status register(ADC_ISR) 451 16.6.2 ADC interrupt enable register(ADC_IER)......................453 1663 ADC control register (ADC CR)..... .455 16.6.4 ADC configuration register(ADC_CFGR) 458 16.6.5 ADC configuration register 2(ADC CFGR2) .462 16.6.6 ADC sample time register1(ADC_SMPR1) 464 16.67 ADC sample time register 2(ADC_SMPR2) 16.6.8 ADC watchdog threshold register 1(ADC_TR1) 465 1669 ADC watchdog threshold register 2(ADC_TR2) 16.6.10 ADC watchdog threshold register 3 (ADC TR3)................ .467 166.11 ADC reqular sequence register 1 (ADC SQR1) 468 16.6.12 ADC regular sequence register 2(ADC_SQR2 469 16613 ADC reaular sequence reaister 3(ADC SOR3) 470 16.6.14 ADC regular sequence register 4(ADC_SQR4) 471 16.615 ADC regular data register(ADC_DR) 16.6.16 ADC injected sequence register(ADC_JSQR) 472 16.6.17 ADC offset y register(ADC_OFRy) 473 16.6.18 ADC injected channel y data register (ADC JDRy)....... 474 16.6.19 ADC Analog Watchdog 2 Configuration Register(ADC_AWD2CR) 475 16.6.20 ADC Analog Watchdog 3 Configuration Register(ADC_AWD3CR) 475 16.6.21 ADC Differential mode Selection Register(ADC_DIFSEL)..... .476 16.6.22 ADC Calibration Factors(ADC_CALFACT) 476 16.7 ADC common registers .477 16.7.1 ADC common status register(ADC_CSR) 477 16.7.2 ADC common control register(ADC_CCR)....................479 1673 Common regular data register for dual mode (ADC CDR) 482 16.7.4 ADC register map 482 Digital-to-analog converter (DAC)........................... 486 17.1 Introduction 486 17.2 DAC main features 486 17.3 DAC implementation......................,........... 487 17.4 DAC functional description................................ 488 17.4.1 DAC block diagram 488 17.42 DAC channel enable 489 17.4.3 DAc data format.........................................489 17 44 DAC conversion ...491 14/1600 RM0394 Rev4 7

Contents RM0394 14/1600 RM0394 Rev 4 16.6.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 451 16.6.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 453 16.6.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 16.6.4 ADC configuration register (ADC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 458 16.6.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 462 16.6.6 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 464 16.6.7 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 465 16.6.8 ADC watchdog threshold register 1 (ADC_TR1) . . . . . . . . . . . . . . . . . 465 16.6.9 ADC watchdog threshold register 2 (ADC_TR2) . . . . . . . . . . . . . . . . . 466 16.6.10 ADC watchdog threshold register 3 (ADC_TR3) . . . . . . . . . . . . . . . . . 467 16.6.11 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 468 16.6.12 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 469 16.6.13 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 470 16.6.14 ADC regular sequence register 4 (ADC_SQR4) . . . . . . . . . . . . . . . . . 471 16.6.15 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 471 16.6.16 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 472 16.6.17 ADC offset y register (ADC_OFRy) . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 16.6.18 ADC injected channel y data register (ADC_JDRy) . . . . . . . . . . . . . . . 474 16.6.19 ADC Analog Watchdog 2 Configuration Register (ADC_AWD2CR) . . 475 16.6.20 ADC Analog Watchdog 3 Configuration Register (ADC_AWD3CR) . . 475 16.6.21 ADC Differential mode Selection Register (ADC_DIFSEL) . . . . . . . . . 476 16.6.22 ADC Calibration Factors (ADC_CALFACT) . . . . . . . . . . . . . . . . . . . . . 476 16.7 ADC common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 16.7.1 ADC common status register (ADC_CSR) . . . . . . . . . . . . . . . . . . . . . 477 16.7.2 ADC common control register (ADC_CCR) . . . . . . . . . . . . . . . . . . . . 479 16.7.3 Common regular data register for dual mode (ADC_CDR) . . . . . . . . . 482 16.7.4 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 17 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 17.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 17.3 DAC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 17.4 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 17.4.1 DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 17.4.2 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 17.4.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 17.4.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

RM0394 Contents 17.45 DAC output voltage 491 17.46 DAC trigger selection 17.4.7 DMA requests 492 17.4.8 Noise generation 493 17.4.9 Triangle-wave generation 17.4.10 DAC channel modes 494 17.4.11 DAC channel buffer calibration 17.4.12 Dual DAC channel conversion (if available)....... 499 17.5 DAC low-power modes 504 17.6 DAC interrupts.... 504 17.7 DAcregisters ........................................... 505 17.7.1 DAC control register(DAC_CR) 505 17.72 DAC software trigger register (DAC_SWTRGR)................ 508 17.7.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1).... 508 177.4 DAC channel1 12-bit left aligned data holding register (DAC DHR12L1)...... 509 17.7.5 DAC channel1 8-bit right aligned data holding register (DAC DHR8R1).,,.,..,..,..,.,,., ...509 17.7.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2). .510 17.7.7 DAC channel2 12-bit left aligned data holding register (DAC DHR12L2) ..510 17.7.8 DAC chan e28-bitight-aliged data hoding register (DAC DHR8R2) .510 17.7.9 .511 17.7.10 Dual DAC 12-bit left aligned data holding register (DAC DHR121D) 511 17.7.11 data holding registe 512 17.7.12 DAC channel1 data output register(DAC_DOR1) 512 17.7.13 DAC channel2 data output register (DAC DOR2)............ ...513 17.7.14 DAC status register(DAC_SR) 513 17.7.15 DAC calibration control register (DAC CCR)............ .515 17.7.16 DAC mode control register (DAC MCR). 515 17.7.17 el 1 sample and hold sample time registe .517 17.7.18 sample and hold sample time register 517 7 RM0394 Rev 4 15/1600

RM0394 Rev 4 15/1600 RM0394 Contents 43 17.4.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 17.4.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 17.4.7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 17.4.8 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 17.4.9 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 17.4.10 DAC channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 17.4.11 DAC channel buffer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 17.4.12 Dual DAC channel conversion (if available) . . . . . . . . . . . . . . . . . . . . 499 17.5 DAC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 17.6 DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 17.7 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 17.7.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 17.7.2 DAC software trigger register (DAC_SWTRGR) . . . . . . . . . . . . . . . . . 508 17.7.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 17.7.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 17.7.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 17.7.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 17.7.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 17.7.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 17.7.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 17.7.10 Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 17.7.11 Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 17.7.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 512 17.7.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 513 17.7.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 17.7.15 DAC calibration control register (DAC_CCR) . . . . . . . . . . . . . . . . . . . 515 17.7.16 DAC mode control register (DAC_MCR) . . . . . . . . . . . . . . . . . . . . . . . 515 17.7.17 DAC channel 1 sample and hold sample time register (DAC_SHSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 17.7.18 DAC channel 2 sample and hold sample time register (DAC_SHSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517