Contents RM0394 6.2.10 Clock security system(CSS) 6.2.11 Clock security system on LSE...............................187 6212 ADC clock ,187 62.13 RTCclock 187 6.2.14 ,188 6.2.15 Watchdog clock 188 6.2.16 Clock-out capability 6.2.17 Intemnal/extemal clock measurement with TIM15IM16 ..189 6218 191 6.3 Low-power modes 191 6.4 RCC registers 193 6.4.1 Clock control register (RCC CR)........... ,193 6.4.2 Intemal clock sources calibration register(RCC_ICSCR) 196 6.43 Clock configuration register (RCC_CFGR) 6.4.4 PLL configuration register (RCC PLLCFGR) 198 PLLSAI1 configuration register(RCC_PLLSAI1CFGR) 201 Clock interrupt enable register(RCC_CIER) 。。。 204 6.4.7 Clock interrupt flag register(RCC CIFR) 206 648 Clock interrupt clear register(RCC_CICR 207 6.4.9 AHB1 peripheral reset register(RCC_AHB1RSTR) 208 6.4.10 AHB2 peripheral reset register(RCC_AHB2RSTR) 209 6.4.11 AHB3 peripheral reset register(RCC_AHB3RSTR) 211 6.4.12 APB1 peripheral reset register 1(RCC APB1RSTR1) 211 64.13 APB1 peripheral reset register 2(RCC_APB1RSTR2) 214 6.4.14 APB2 peripheral reset register(RCC_APB2RSTR) 215 6.415 AHB1 peripheral clock enable register(RCC AHB1ENR) 216 6.4.16 AHB2 peripheral clock enable register(RCC_AHB2ENR) 218 6.4.17 AHB3 peripheral clock enable register(RCC AHB3ENR)...... 219 6.4.18 APB1 peripheral clock enable register 1(RCC_APB1ENR1) 6.4.19 APB1 peripheral clock enable register 2(RCC_APB1ENR2) 6.4.20 APB2 peripheral clock enable register(RCC_APB2ENR). .224 6.4.21 ocks enable in Sleep and Stop modes register 225 6.422 enable in Sleep and Stop modes registe AHB2SMENR) 226 6.4.23 cks AHB3SMENR enable in Sleep and Stop modes registe .228 6/1600 RM0394 Rev 4 7
Contents RM0394 6/1600 RM0394 Rev 4 6.2.10 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.2.11 Clock security system on LSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.12 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.13 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.14 Timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.2.15 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.2.16 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.2.17 Internal/external clock measurement with TIM15/TIM16 . . . . . . . . . . . 189 6.2.18 Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy) . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.4 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.4.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.4.2 Internal clock sources calibration register (RCC_ICSCR) . . . . . . . . . . 196 6.4.3 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 196 6.4.4 PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . . . . . 198 6.4.5 PLLSAI1 configuration register (RCC_PLLSAI1CFGR) . . . . . . . . . . . 201 6.4.6 Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 204 6.4.7 Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 206 6.4.8 Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 207 6.4.9 AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . . . . . 208 6.4.10 AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . . . . . 209 6.4.11 AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . . . . . 211 6.4.12 APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . . . . . 211 6.4.13 APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . . . . . 214 6.4.14 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 215 6.4.15 AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . . . . . 216 6.4.16 AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . . . . . 218 6.4.17 AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . . . . . . . 219 6.4.18 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 220 6.4.19 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 222 6.4.20 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 224 6.4.21 AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 6.4.22 AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.4.23 AHB3 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
RM0394 Contents 6.4.24 8pRe8ieEaenensepansapmoteseer1 .228 6.4.25 ble and opmodes .231 6.4.26 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC APB2SMENR) 233 6.4.27 Peripherals independent clock configuration register(RCC_CCIPR) 234 6.4.28 Backup domain control register (RCC BDCR)..................237 6420 Controlstatus register(RCC CSR) 239 6.4.30 Clock recovery RC register(RCC_CRRCR)..... 241 6.4.31 Peripherals independent clock configuration register(RCC_CCIPR2)242 6432 RCC register map 242 Clock recovery system (CRS)...............................247 7.1 Introduction 247 7.2 CRS main features. 247 7.3 CRS functional description................................... 248 7.3.1 CRS block diagram 248 7.32 Synchronization input 248 7.3.3 Frequency error measurement 249 73.4 Frequency error evaluation and automatic trimming 250 7.3.5 CRS initialization and configuration ......................... 250 7.4 CRS low-power modes. 251 7.5 CRS interrupts.......................................... 251 7.6 CRS registers 252 7.6.1 CRS control register(CRS CR)..... ,252 7.6.2 CRS configuration register (CRS_CFGR) 253 7.6.3 CRS interrupt and status register (CRS ISR).................. .254 764 CRS interupt flag clear register(CRS ICR) .256 7.6.5 CRS register map 257 8 General-purpose l/os (GPIO)............................... 258 8.1 Introduction 258 8.2 GPIO main features 258 8.3 GPIO functional description 258 8.3.7 General-purpose /(GPIO 261 8.3.2 1/O pin alternate function multiplexer and mapping........... ,261 7 RM0394 Rev4 71600
RM0394 Rev 4 7/1600 RM0394 Contents 43 6.4.24 APB1 peripheral clocks enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 6.4.25 APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 6.4.26 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 6.4.27 Peripherals independent clock configuration register (RCC_CCIPR) . 234 6.4.28 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 237 6.4.29 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 6.4.30 Clock recovery RC register (RCC_CRRCR) . . . . . . . . . . . . . . . . . . . . 241 6.4.31 Peripherals independent clock configuration register (RCC_CCIPR2) 242 6.4.32 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 7 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 7.2 CRS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 7.3 CRS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 7.3.1 CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 7.3.2 Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 7.3.3 Frequency error measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 7.3.4 Frequency error evaluation and automatic trimming . . . . . . . . . . . . . . 250 7.3.5 CRS initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 7.4 CRS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 7.5 CRS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 7.6 CRS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.6.1 CRS control register (CRS_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.6.2 CRS configuration register (CRS_CFGR) . . . . . . . . . . . . . . . . . . . . . . 253 7.6.3 CRS interrupt and status register (CRS_ISR) . . . . . . . . . . . . . . . . . . . 254 7.6.4 CRS interrupt flag clear register (CRS_ICR) . . . . . . . . . . . . . . . . . . . . 256 7.6.5 CRS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 8 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 8.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 8.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 8.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 8.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 261
Contents RM0394 8.3.3 O port control registers 262 8.3.4 l/o port data registers.....................................262 8.3.5 V/O data bitwise handling ,262 8.36 GPIO locking mechanism 263 8.3.7 1/O alternate function input/output........................... 263 8.3.8 Extemnal interrupt/wakeup lines 263 83.9 Input configuration,,,,,,,,,,,,,,,,,,,,,,,,, 264 8.3.10 Output configuration 264 8311 Altemnate function configuration 265 8.3.12 Analog configuration.................................... 8313 Using the HSE or LSE oscillator pins as GPIOs … 266 8.3.14 Using the GPIO pins in the RTC supply domain 266 8.3.15 Using PH3 as GPIO 267 8.4 GPIO registers........................ 267 8.4.1 GPIO port mode register(GPIOx_MODER)(x=A to E and H). 267 8.4.2 GPIO port output type register(GPIOx_OTYPER)(x=A to E and H)268 8.4.3 268 8.4.4 268 8.4.5 GPIO port input data register (GPIOx IDR)(x =A to E and H)......269 8.4.6 GPIO port output data register(GPIOx_ODR)(x=A to E and H) ..269 8.47 GPIO port bit set/reset register (GPIOx_BSRR)(x=Ato E and H) 8.4.8 GPIO port configuration lock register(GPIOx_LCKR) (=Ato Eand H)....................................... 270 8.4.9 GPIO alternate function low register(GPIOx_AFRL) (x=A to E and H）.................... 271 8.4.10 GPIO alternate function high register(GPIOx_AFRH) (x =A to E and H)......... .272 8411 GPIO port bit reset register(GPIOx_BRR)(x=A to E and H)......273 84.12 GPIO register map 274 9 System configuration controller (SYSCFG)....................276 9.1 SYSCFG main features 。。。。 276 9.2 SYSCFG registers................ 276 9.2.1 SYSCFG memory remap register(SYSCFG_MEMRMP)...... 276 9.22 SYSCFG configuration register 1(SYSCFG CFGR1) ,..277 9.2.3 errupt configuration register1 .278 8/1600 RM0394 Rev 4 7
Contents RM0394 8/1600 RM0394 Rev 4 8.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 8.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 8.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 8.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 8.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 8.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 266 8.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 266 8.3.15 Using PH3 as GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 8.4 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A to E and H) . . . . . . 267 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A to E and H) 268 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A to E and H) . . . . . . 269 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A to E and H) . . . . 269 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A to E and H) . . 270 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to E and H) . . . . . . 273 8.4.12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 9 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 276 9.1 SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.2 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 276 9.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 277 9.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
RM0394 Contents 9.2.4 SYSCFG extemnal interrupt configuration register 2 (SYSCFG EXTICR2) ..280 9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG EXTICR3) 281 926 SYSCFG extemnal interrupt configuration register 4 (SYSCFG EXTICR4) 283 9.2.7 SYSCFG SRAM2 control and status register(SYSCFG_SCSR) 284 9.2.8 SYSCFG configuration register 2(SYSCFG CFGR2)............285 929 SYSCFG SRAM2 write protection register(SYSCFG SWPR).. ..286 9.2.10 SYSCFG SRAM2 key register(SYSCFG_SKR) 286 9.2.11 SYSCFG register map. .287 Peripherals interconnect matrix 288 10.1 Introduction............ 288 10.2 Connection summary.................................... 288 10.3 Interconnection details 289 10.3.1 2er (TM/TM2/M15/TM1)tomer (TIM1/M2TM15/TM1) 10.3.2 From timer (TIM1/TIM2/TIM6/TIM15)and EXTI to ADC (ADC1).....290 10.3.3 From ADC(ADC1)to timer (TIM1) 290 10.3.4 From timer (TIM2/TIM6/TIM7)and EXTI to DAC(DAC1/DAC2) 10.3.5 From HSE,LSE,LSI.MSI.MCO.RTC to timer(TIM2/TIM15/TIM16).291 103.6 From RTC,COMP1,COMP2 to low-power timer(LPTIM1/LPTIM2)..291 10.3.7 2. 292 10.3.8 From ADC(ADC1)to ADC(ADC2)..........................292 10.3.9 From USB to timer (TIM2) 292 10.3.10 nal analog source to ADC (ADC1)and OPAMP ,293 10.3.11 1/COMP2)to timers 293 10.312 From system errors to timers (TIM1/TIM15/TIM16) 294 10.3.13 From timers (TIM16)to IRTIM.... .294 Direct memory access controller(DMA) 295 11.1 Introduction 295 11.2 DMA main features........... 295 11.3 DMA implementation 296 11.3.1 DMA1 and DMA2 296 7 RM0394 Rev4 9/1600
RM0394 Rev 4 9/1600 RM0394 Contents 43 9.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 9.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . 284 9.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 285 9.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR) . . . . . . 286 9.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . . . . . . . . . . . . . . 286 9.2.11 SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 10 Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.2 Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 10.3 Interconnection details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 10.3.1 From timer (TIM1/TIM2/TIM15/TIM16) to timer (TIM1/TIM2/TIM15/TIM16) 289 10.3.2 From timer (TIM1/TIM2/TIM6/TIM15) and EXTI to ADC (ADC1) . . . . . 290 10.3.3 From ADC (ADC1) to timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 10.3.4 From timer (TIM2/TIM6/TIM7) and EXTI to DAC (DAC1/DAC2) . . . . . 290 10.3.5 From HSE, LSE, LSI, MSI, MCO, RTC to timer (TIM2/TIM15/TIM16) . 291 10.3.6 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2) . . 291 10.3.7 From timer (TIM1/TIM2/TIM15) to comparators (COMP1/COMP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.3.8 From ADC (ADC1) to ADC (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.3.9 From USB to timer (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.3.10 From internal analog source to ADC (ADC1) and OPAMP (OPAMP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.3.11 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM15/TIM16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.3.12 From system errors to timers (TIM1/TIM15/TIM16) . . . . . . . . . . . . . . . 294 10.3.13 From timers (TIM16) to IRTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 295 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 11.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 11.3 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 11.3.1 DMA1 and DMA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Contents RM0394 1132 DMA request mapping 296 11.4 DMA functional description. 299 114.1 DMA block diagram 114.2 DMA transfers. 309 114.3 DMA arbitration 301 14.4 DMA channels 302 11.4.5 DMA data width,alignment and endianness................ .306 1146 DMA error management 307 11.5 DMA interrupts....,.................. 。。。。。。 308 11.6 DMA registers 308 11.6.1 DMA interrupt status register(DMA_ISR). 308 11.6.2 DMA interrupt flag clear register(DMA_IFCR) 311 11.6.3 DMA channel x configuration register (DMA CCRx)........ 312 1164 DMA channel x number of data to transfer register (DMA CNDTRx).315 11.6.5 DMA channel x peripheral address register (DMA_CPARx) 11.6.6 DMA channel x memory address register(DMA_CMARx) .........316 116 7 DMA channel selection register (DMA CSELR) 317 11.6.8 DMA register map and reset values 317 Nested vectored interrupt controller(NVIC)................. 320 12.1 NVIC main features........................................ 320 12.2 SysTick calibration value register 320 12.3 Interrupt and exception vectors 321 13 Extended interrupts and events controller(EXTI)............... 325 13.1 Introduction..... 325 13.2 EXTI main features........................................ 325 13.3 EXTI functional description 325 13.3.1 EXTI block diagram .326 1332 Wakeup event management 13.3.3 Peripherals asynchronous Interrupts...................... 13.3.4 Hardware interrupt selection 13.35 Hardware event selection 327 13.3.6 Software interrupt/event selection........................... .327 13.4 EXTI interrupt/event line mapping............................ 327 13.5 EXTI registers 330 10/1600 RM0394 Rev4 7
Contents RM0394 10/1600 RM0394 Rev 4 11.3.2 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 11.4 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 11.4.1 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 11.4.2 DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 11.4.3 DMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 11.4.4 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 11.4.5 DMA data width, alignment and endianness . . . . . . . . . . . . . . . . . . . . 306 11.4.6 DMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 11.5 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 11.6 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 11.6.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 308 11.6.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 311 11.6.3 DMA channel x configuration register (DMA_CCRx) . . . . . . . . . . . . . . 312 11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) . 315 11.6.5 DMA channel x peripheral address register (DMA_CPARx) . . . . . . . . 315 11.6.6 DMA channel x memory address register (DMA_CMARx) . . . . . . . . . 316 11.6.7 DMA channel selection register (DMA_CSELR) . . . . . . . . . . . . . . . . . 317 11.6.8 DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 317 12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 320 12.1 NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 12.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 12.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 13 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . 325 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 13.2 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 13.3 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 13.3.1 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 13.3.2 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 13.3.3 Peripherals asynchronous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.3.4 Hardware interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.3.5 Hardware event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.3.6 Software interrupt/event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.4 EXTI interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 13.5 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330