21nAb9nahPCane 2.1 About the functions Block diagram showing the structure of the Cortex-M4 processor. Cortex-M4 processo Nested Cortex-M4 core Embedde Trace (ETM) AHB Trace Port (AHB-AP Bus Matri (TPIU) 5Yatem PPB APB interface Optional component Figure 2-1 Cortex-M4 block diagram ARM100166000100en opygh1ghtsv 2-21
2.1 About the functions Block diagram showing the structure of the Cortex-M4 processor. ‡ ‡ Nested Vectored Interrupt Controller (NVIC) Bus Matrix Cortex-M4 processor Trace Port ‡ CoreSight Interface ROM table Serial-Wire or JTAG Debug Interface ICode AHB-Lite instruction interface DCode AHB-Lite data interface System AHB-Lite system interface PPB APB debug system interface Interrupts and power control Wake-up Interrupt Controller (WIC) Serial-Wire or JTAG Debug Port (SW-DP or SWJ-DP) ‡ Embedded Trace Macrocell (ETM) ‡ ‡ Flash Patch Breakpoint (FPB) ‡ Memory Protection Unit (MPU) ‡ Data Watchpoint and Trace (DWT) ‡ AHB Access Port (AHB-AP) ‡ Instrumentation Trace Macrocell (ITM) Trace Port Interface Unit (TPIU) ‡ Optional component Cortex-M4 core ‡ Floating Point Unit (FPU) Figure 2-1 Cortex-M4 block diagram 2 Functional Description 2.1 About the functions ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 2-21 Non-Confidential
252rPe06aReg Processor features ve C油oVic features. The complete processor features list comprises A low gate count processor core,with low latency interrupt processing that has: A subset of the Thumb instruction set,defined in the ARMv7-M Architecture Reference Manal Banked Stack Pointer(SP). Hardware integer divide instructions,SDIV and UDIV -Handler and Thread modes. -Thumb and Debug states. -Support for interruptible-continued instructions LDM,STM,PUSH,and PoP for low interrupt latency -Automatic processor state saving and restoration for low latency Interrupt Service Routine(ISR) entry and exit n byte-invariant or little-endian accesses )data-prenrio precision(Fused MAC). ororconversion.subiraction.multipication ith opional accumulae pled th nregisters,also add sable as 16 double- ord registers Nested va ad l sely integrated with the processor core to achieve low-lateney interrupt proces sing features include- -External interrupts.configurable from I to 240 -Bits of priority configurable from 3 to -Dynamic reprioritization of inter Priority a interrupt levels. Support for tail-chaining and late arrival of interrupts This enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. Processor state automatically saved on interrupt entry,and restored on interrupt exit,with no ction overhea Optiona -up Interrupt C roller (WIC),providing ultra-l -power sleep mode suppor ory Protection Unit(MPU).An opti or memory protection,including on Disd e(SRD),enabling efficient use of memory regions The ability to enable a background region that implements thed efault memory map attributes Bus interfaces High-performance Bus-Lite(AHB-Lite)ine rfaces:ICode,DCode,and System heral rus (PpB)hased on Ad D. ral Bus(APB)interface Bit-band upport atomi bit-band and read operation ofwrite data ve acce Low ARM100166_0001_00_en 2-22
2.2 Processor features The Cortex-M4 processor includes a low gate count processor core with low latency interrupt processing, an optional Floating Point Unit (FPU), a Nested Vectored Interrupt Controller (NVIC), and other features. The complete processor features list comprises: • A low gate count processor core, with low latency interrupt processing that has: — A subset of the Thumb instruction set, defined in the ARM® v7-M Architecture Reference Manual. — Banked Stack Pointer (SP). — Hardware integer divide instructions, SDIV and UDIV. — Handler and Thread modes. — Thumb and Debug states. — Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low interrupt latency. — Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and exit. — Support for ARMv6 big-endian byte-invariant or little-endian accesses. — Support for ARMv6 unaligned accesses. • Optional Floating Point Unit (FPU) providing: — 32-bit instructions for single-precision (C float) data-processing operations. — Combined Multiply and Accumulate instructions for increased precision (Fused MAC). — Hardware support for conversion, addition, subtraction, multiplication with optional accumulate, division, and square-root. — Hardware support for denormals and all IEEE rounding modes. — 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers. — Decoupled three stage pipeline. • Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low-latency interrupt processing. Features include: — External interrupts, configurable from 1 to 240. — Bits of priority, configurable from 3 to 8. — Dynamic reprioritization of interrupts. — Priority grouping. This enables selection of preempting interrupt levels and non preempting interrupt levels. — Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. — Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. — Optional Wake-up Interrupt Controller (WIC), providing ultra-low-power sleep mode support. • Memory Protection Unit (MPU). An optional MPU for memory protection, including: — Eight memory regions. — Sub Region Disable (SRD), enabling efficient use of memory regions. — The ability to enable a background region that implements the default memory map attributes. • Bus interfaces: — Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, DCode, and System bus interfaces. — Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface. — Bit-band support that includes atomic bit-band write and read operations. — Memory access alignment. — Write buffer for buffering of write data. — Exclusive access transfers for multiprocessor systems. • Low-cost debug solution that features: 2 Functional Description 2.2 Processor features ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 2-22 Non-Confidential
252Po0063n8 -Debug access to all memory and registers in the system,including access to memory-mapped -Serial Wire Debug Port (SW-DP)or Serial Wire JTAG Debug Port(SWJ-DP)debug access -Optional Flash Patch and Breakpoint(FPB)unit for implementing breakpoints and code patches -Optional Da a Watchpoint and Trace(DWT)unit for implementing watchpoints,data tracing.and em profiling. Optional stm mentation Trace Mac cell(ITM)for suppor of(style debugging or bridging to a Trace Port Analyzer (TPA) e Optional Em () ce(ETM)for ARM100166000100en opygh1 nghts 2-23
— Debug access to all memory and registers in the system, including access to memory-mapped devices, access to internal core registers when the core is halted, and access to debug control registers even while SYSRESETn is asserted. — Serial Wire Debug Port (SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP) debug access. — Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches. — Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling. — Optional Instrumentation Trace Macrocell (ITM) for support of printf() style debugging. — Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA), including Single Wire Output (SWO) mode. — Optional Embedded Trace Macrocell (ETM) for instruction trace. 2 Functional Description 2.2 Processor features ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 2-23 Non-Confidential
2Fneong8iegag 2.3 Interfaces 测I M ETM to the processor,and an Advanced High-performance Bus Access Port(AHB-AP)interface for debug accesses This section contains the following subsections .2.3.I Bus interfaces on page 2-24. ·2.3.2 ETM interface on e.35 2.3.4 Debug Port AHB-AP interface on 2.3.1 Bus interfaces The Cortex-M4 processor contains three external advanced high-performance bus (ahb)-Lite bus interfaces and one Advanced Peripheral Bus(APB)interface. The processor matches the AMBA3 specification except for maintaining control information during waited transte The AN BA 3 A HB Lite Protocol states at when the slave is requesting wait states the transter type,excep ng cas the fer type from IDLE toNONSEQ transfer with a fixe ength burst,the master can change the transfer type from BUSY t .On a BUSY transfer with an undefined length burst,the master can change the transfer type from BUSY to any other transfer type. The not match this definition because it might change the access type from SEQ ndng a w addre retracted might not be requested again.This cancels the outstanding transfer that has not occurred because the previous access is wait-stated and awaiting completion.This is done so that the processor can have a lower interrupt latency and higher performance in wait-stated systems by retracting accesses that are no longer required To achieve complete compliance with the AMBA 3 specification you can implement the design with the AHB_CONST_CTRL parameter set to 1.This ensures that when transfers are issued during a wait-stated response they are never re ted or modified and the original transfer is onore .The consequence o core might decrease for wait-stated systems as ICode memory interface Instruction fetches from Code memory space.0xe0000000 to 0x1FFFFFFC.are performed over the 32-bit AHB-Lite bus. DCode memory interface B-LI sses to Code memory space.x,are performed over the The Code memory space available is dependent on the implementation.Core data accesses have a highe priority than debug accesses on this bus.This means that debug accesses are waited until core accesses have completed when there are simultaneous core and debug access to this bus. ARM100166_0001_00_en 2-24
2.3 Interfaces The processor incorporates three external bus interfaces, an ETM interface that allows the connection of an Embedded Trace Macrocell, an AHB Trace Macrocell interface that enables simple connection of an ETM to the processor, and an Advanced High-performance Bus Access Port (AHB-AP) interface for debug accesses. This section contains the following subsections: • 2.3.1 Bus interfaces on page 2-24. • 2.3.2 ETM interface on page 2-25. • 2.3.3 AHB Trace Macrocell interface on page 2-26. • 2.3.4 Debug Port AHB-AP interface on page 2-26. 2.3.1 Bus interfaces The Cortex-M4 processor contains three external Advanced High-performance Bus (AHB)-Lite bus interfaces and one Advanced Peripheral Bus (APB) interface. The processor matches the AMBA 3 specification except for maintaining control information during waited transfers. The AMBA 3 AHB-Lite Protocol states that when the slave is requesting wait states the master must not change the transfer type, except for the following cases: • On an IDLE transfer, the master can change the transfer type from IDLE to NONSEQ. • On a BUSY transfer with a fixed length burst, the master can change the transfer type from BUSY to SEQ. • On a BUSY transfer with an undefined length burst, the master can change the transfer type from BUSY to any other transfer type. The processor does not match this definition because it might change the access type from SEQ or NONSEQ to IDLE during a waited transfer. The processor might also change the address or other control information and therefore request an access to a new location. The original address that was retracted might not be requested again. This cancels the outstanding transfer that has not occurred because the previous access is wait-stated and awaiting completion. This is done so that the processor can have a lower interrupt latency and higher performance in wait-stated systems by retracting accesses that are no longer required. To achieve complete compliance with the AMBA 3 specification you can implement the design with the AHB_CONST_CTRL parameter set to 1. This ensures that when transfers are issued during a wait-stated response they are never retracted or modified and the original transfer is honored. The consequence of setting this parameter is that the performance of the core might decrease for wait-stated systems as a result of the interrupt and branch latency increasing. ICode memory interface Instruction fetches from Code memory space, 0x00000000 to 0x1FFFFFFC, are performed over the 32-bit AHB-Lite bus. The Debugger cannot access this interface. All fetches are word-wide. The number of instructions fetched per word depends on the code running and the alignment of the code in memory. DCode memory interface Data and debug accesses to Code memory space, 0x00000000 to 0x1FFFFFFF, are performed over the 32-bit AHB-Lite bus. The Code memory space available is dependent on the implementation. Core data accesses have a higher priority than debug accesses on this bus. This means that debug accesses are waited until core accesses have completed when there are simultaneous core and debug access to this bus. 2 Functional Description 2.3 Interfaces ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 2-24 Non-Confidential
2Funciong9ensrg8eg Control logic in this interface converts unaligned data and debug accesses into two or three aligned accesses,depending on the size and alignment of the unaligned access.This stalls any subsequent data or debug access until the unaligned access has completed. Note- ARM strongly recommends that any external arbitration between the ICode and DCode AHB bus interfaces ensures that DCode has a higher priority than ICode. System interface 0 to @xDFFFFFFF and For simultaneous accesses to the 32-bit AHB-Lite bus,the arbitration order in decreasing priority is: .Data ac Instruction and vector fetches. ·Debug. The system bus interface contains control logic to handle unaligned accesses,FPB remapped accesses, bit-band accesses,and pipelined instruction fetches. Private Peripheral Bus(PPB) Core data accesses have higher priority than deb ses so dehug a sses are waited until core accesses have completed when there are simultaneous core and debug accesses to this bus.Only the address bits necessary to decode the External PPB space are supported on this interface. The Exter mal) nd a numbe CoreSigh system peripherals.ARM recommends that system peripherals are placed in suitable Device type areas of the System bus address space,with use of an AHB2APB protocol converter for APB-based devices. Limitations of the EPPB space are: It is accessible in nrivileged mode only .It is accessed in little-endian fashion irrespective of the data endianness setting of the processor. Accesses behave as Strongly Ordered. Unaligned accesses have UNPREDICTABLE results Only 32.hit data accesses are supnorted .It isaccessible from the Debug Port and the local processor,but not from any other processor in the system. 2.3.2 ETM interface mo的icoainoitikEnocmeapmtahd See the ARM Embedded Trace Macrocell Architecture Specification ARM100166000100en opygh1 nghts 2-25
Control logic in this interface converts unaligned data and debug accesses into two or three aligned accesses, depending on the size and alignment of the unaligned access. This stalls any subsequent data or debug access until the unaligned access has completed. Note ARM strongly recommends that any external arbitration between the ICode and DCode AHB bus interfaces ensures that DCode has a higher priority than ICode. System interface Instruction fetches and data and debug accesses to address ranges 0x20000000 to 0xDFFFFFFF and 0xE0100000 to 0xFFFFFFFF are performed over the 32-bit AHB-Lite bus. For simultaneous accesses to the 32-bit AHB-Lite bus, the arbitration order in decreasing priority is: • Data accesses. • Instruction and vector fetches. • Debug. The system bus interface contains control logic to handle unaligned accesses, FPB remapped accesses, bit-band accesses, and pipelined instruction fetches. Private Peripheral Bus (PPB) Data and debug accesses to external PPB space, 0xE0040000 to 0xE00FFFFF, are performed over the 32- bit Advanced Peripheral Bus (APB) bus. The Trace Port Interface Unit (TPIU) and vendor specific peripherals are on this bus. Core data accesses have higher priority than debug accesses, so debug accesses are waited until core accesses have completed when there are simultaneous core and debug accesses to this bus. Only the address bits necessary to decode the External PPB space are supported on this interface. The External PPB (EPPB) space, 0xE0040000 up to 0xE0100000, is intended for CoreSight-compatible debug and trace components, and has a number of irregular limitations that make it less useful for regular system peripherals. ARM recommends that system peripherals are placed in suitable Device type areas of the System bus address space, with use of an AHB2APB protocol converter for APB-based devices. Limitations of the EPPB space are: • It is accessible in privileged mode only. • It is accessed in little-endian fashion irrespective of the data endianness setting of the processor. • Accesses behave as Strongly Ordered. • Unaligned accesses have UNPREDICTABLE results. • Only 32-bit data accesses are supported. • It is accessible from the Debug Port and the local processor, but not from any other processor in the system. 2.3.2 ETM interface The ETM interface enables simple connection of the ETM-M4 to the processor, and provides a channel for instruction trace to the ETM. See the ARM® Embedded Trace Macrocell Architecture Specification. 2 Functional Description 2.3 Interfaces ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 2-25 Non-Confidential