1.5 Product documentation Documentation provided with this product includes a Technical Reference Manual,an Integration and Implementation manual,together with design flow,architecture,and protocol information. Reference manals on page 1-16. Architectre and protocol information on page 1-17 1.5.1 Reference manuals This processor user reference mate Technical Reference Manual I he rechm erence Ma des scribes th functionality and the effects of functional behavior in the TRM might not be relevant because of thew y that the Cortex-M4 processor is implemented and integrated.If you are programming the Cortex-M4 processor then contact: The implementer to determine -The build configuration of the implementation -What integration,if any,was performed before implementing the processor The integrator to determine the pin configuration of the SoC that you are using n manual (im)de The available build configuration options and related issues in selecting them How to configure the re fer level (rtl)with the build co figuration options. How to e the tion ki and describes the pins that the integrator must tie off to configure the macrocell for the required integration How to implement the processor into your design.This includes floorplanning guidelines Design or Test(DFT)information.and how to perform netlist dynamic verification on th The ARM product deliverables include reference scripts and information about using them to implement vour design. Reference methodology documentation from your EDA tools vendor complements the IIM. The IIM is a confidential book that is only available to licensees ETM-M4 Technical Reference Manual he ETM- IRMd s the func nality and behavior of ex-M4 proc ARM100166000100en Copyright010.213015ARM.All nghtsreseved 1-16
1.5 Product documentation Documentation provided with this product includes a Technical Reference Manual, an Integration and Implementation manual, together with design flow, architecture, and protocol information. This section contains the following subsections: • 1.5.1 Reference manuals on page 1-16. • 1.5.2 Design Flow on page 1-17. • 1.5.3 Architecture and protocol information on page 1-17. 1.5.1 Reference manuals This product is supplied with a complete set of reference manuals that describe processor functionality, build configuration options, and reference material that ARM partners might want to include in their own processor user guides. Technical Reference Manual The Technical Reference Manual (TRM) describes the functionality and the effects of functional options on the behavior of the Cortex-M4 processor. It is required at all stages of the design flow. Some behavior described in the TRM might not be relevant because of the way that the Cortex-M4 processor is implemented and integrated. If you are programming the Cortex-M4 processor then contact: • The implementer to determine: — The build configuration of the implementation. — What integration, if any, was performed before implementing the processor. • The integrator to determine the pin configuration of the SoC that you are using. Integration and Implementation Manual The Integration and Implementation Manual (IIM) describes: • The available build configuration options and related issues in selecting them. • How to configure the Register Transfer Level (RTL) with the build configuration options. • How to integrate the processor into a SoC. This includes a description of the integration kit and describes the pins that the integrator must tie off to configure the macrocell for the required integration. • How to implement the processor into your design. This includes floorplanning guidelines, Design for Test (DFT) information, and how to perform netlist dynamic verification on the processor. • The processes to sign off the integration and implementation of the design. The ARM product deliverables include reference scripts and information about using them to implement your design. Reference methodology documentation from your EDA tools vendor complements the IIM. The IIM is a confidential book that is only available to licensees. ETM-M4 Technical Reference Manual The ETM-M4 TRM describes the functionality and behavior of the Cortex-M4 Embedded Trace Macrocell. It is required at all stages of the design flow. Typically the ETM-M4 is integrated with the Cortex-M4 processor prior to implementation as a single macrocell. 1 Introduction 1.5 Product documentation ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 1-16 Non-Confidential
15Prduco Cortex-M4 User Guide Reference Material Each chapter in this reference material might correspond to a section in the User Guide. -v crterenc materalmht correspondoa chaper hs However.you can organize this material in any way.subiect to the conditions of the license agreement under which ARM supplied the material. 1.5.2 Design Flow The design flow of the processor includes steps for implementation,integration,and programming. These steps must be completed before the processor is ready for operation. Implementation The implementer configures and synthesizes the RTL emented design into a SoC.This includes connecting it toa memory system and periph als Programming and test te'require dev elops the software required to configure and initialize the processor erequired application sofware Each stage in the process can be performed by a different party.Implementation and integration choices affect the behavior and features of the processor. team ntegrates the processor b esign AicCTocelGaishcniniegred.possbyyaseparaietea Mn or part d,to pro The operation of the final device depends on: Build configu The imnlem enter chooses the ontions that affect how the rtl source files a The inelude r elue o hat one more oftemm trequency,and features of the resulting macrocell. These configurations affect the star nfig ration is made They can also limit the options available to the software. Software configuration ssor by programming particular values into registers.This -Note efined featres that are appli able to build nfiguration options selected.Reference to n enabled feature means one that has aso been configured by software. 1.5.3 Architecture and protocol information pes6eao应 This book complements architecture reference manuals.architecture specifications.protocol specifications,and relevant external standards,it does not duplicate information from these sources. ARM100166000100en opygh1 nghts 1-17
Cortex-M4 User Guide Reference Material This document provides reference material that ARM partners can configure and include in a User Guide for an ARM Cortex-M4 processor. Typically: • Each chapter in this reference material might correspond to a section in the User Guide. • Each top-level section in this reference material might correspond to a chapter in the User Guide. However, you can organize this material in any way, subject to the conditions of the license agreement under which ARM supplied the material. 1.5.2 Design Flow The design flow of the processor includes steps for implementation, integration, and programming. These steps must be completed before the processor is ready for operation. The processor is delivered as synthesizable RTL. Before it can be used in a product, it must go through the following process: Implementation The implementer configures and synthesizes the RTL. Integration The integrator connects the implemented design into a SoC. This includes connecting it to a memory system and peripherals. Programming The system programmer develops the software required to configure and initialize the processor, and tests the required application software. Each stage in the process can be performed by a different party. Implementation and integration choices affect the behavior and features of the processor. For MCUs, often a single design team integrates the processor before synthesizing the complete design. Alternatively, the team can synthesize the processor on its own or partially integrated, to produce a macrocell that is then integrated, possibly by a separate team. The operation of the final device depends on: Build configuration The implementer chooses the options that affect how the RTL source files are pre-processed. These options usually include or exclude logic that affects one or more of the area, maximum frequency, and features of the resulting macrocell. Configuration inputs The integrator configures some features of the processor by tying inputs to specific values. These configurations affect the start-up behavior before any software configuration is made. They can also limit the options available to the software. Software configuration The programmer configures the processor by programming particular values into registers. This affects the behavior of the processor. Note This manual refers to implementation-defined features that are applicable to build configuration options. Reference to a feature that is included means that the appropriate build and pin configuration options are selected. Reference to an enabled feature means one that has also been configured by software. 1.5.3 Architecture and protocol information The processor complies with, or implements, specifications described in ARM, bus, debug, and other architecture reference manuals. This book complements architecture reference manuals, architecture specifications, protocol specifications, and relevant external standards; it does not duplicate information from these sources. 1 Introduction 1.5 Product documentation ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 1-17 Non-Confidential
15Poaaadchmei ARM architecture The processor implements the ARMv7E-M architecture profile See the ARMv7-M Architecnure Reference Mamal Bus architecture implementsntefc fr CoreSih nd oher devug components ing tM The .The ARMP AMBA*3 AHB-Lite Protocol (v1.0). .The ARM AMBA3 APB Protocol Specification. Debug The debug features of the processor implement the ARM debug interface architecture. See the ARM Debug Interface v5 Architecture Specification. Embedded Trace Macrocell The trace features of the processor implement the ARM Embedded Trace Macrocell architecture. See the ARM Embedded Trace Macrocell Architecture Specification. Floating Point Unit The Cortex-M4 FPU implements ARMv7E-M architecture with FPv4-SP extensions. It provides floating-point computation functionality that is compliant with the ANSI/IEEE Sd 754-008. IEEE Standard for Binary Floating-Point Arithmetic.See the ARMy7M Architecture Reference Manual Related references Chapter 7 Floating-Point Unit on page 7-65. ARM100166_0001_00_en coapy7gne20o9,2010,2018305AdMAWngses9ned 1-18
ARM architecture The processor implements the ARMv7E-M architecture profile. See the ARM® v7-M Architecture Reference Manual. Bus architecture The processor implements an interface for CoreSight and other debug components using the AMBA 3 APB protocol. The processor provides three primary bus interfaces implementing a variant of the AMBA 3 AHB-Lite protocol. See: • The ARM® AMBA® 3 AHB-Lite Protocol (v1.0). • The ARM® AMBA® 3 APB Protocol Specification. Debug The debug features of the processor implement the ARM debug interface architecture. See the ARM® Debug Interface v5 Architecture Specification. Embedded Trace Macrocell The trace features of the processor implement the ARM Embedded Trace Macrocell architecture. See the ARM® Embedded Trace Macrocell Architecture Specification. Floating Point Unit The Cortex-M4 FPU implements ARMv7E-M architecture with FPv4-SP extensions. It provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic. See the ARM® v7M Architecture Reference Manual. Related references Chapter 7 Floating-Point Unit on page 7-65. 1 Introduction 1.5 Product documentation ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 1-18 Non-Confidential
16Pnodaetoe 1.6 Product revisions A description of the differences in functionality between product revisions. Differences in functionality between rop0 and rop1 In summary,the differences in functionality include: New implementation option to ensure constant AHB control during wait-stated transfers. ARM100166000100en opygh1 nghts 1-19
1.6 Product revisions A description of the differences in functionality between product revisions. Differences in functionality between r0p0 and r0p1 In summary, the differences in functionality include: • New implementation option to ensure constant AHB control during wait-stated transfers. 1 Introduction 1.6 Product revisions ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 1-19 Non-Confidential
Chapter 2 Functional Description This chapter introduces the Cortex-M4 processor and its extemal interfaces. It contains the following sections: .2.I About the fimctions on page 2-21. .2.2 Processor features on page 2-22. 2.3 Interfaces on page 2-24. ARM100166_0001_00._en Copgh210 2-20
Chapter 2 Functional Description This chapter introduces the Cortex-M4 processor and its external interfaces. It contains the following sections: • 2.1 About the functions on page 2-21. • 2.2 Processor features on page 2-22. • 2.3 Interfaces on page 2-24. ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 2-20 Non-Confidential