2Funcong8icgag 2.3.3 AHB Trace Macrocell interface The AHB Trace Macrocell (HTM)interface enables a simple connection of the AHB trace macrocell to the processor,and provides a channel for the data trace to the HTM. supply trace data.Sce the AR-MArchitechre Reference Manal 2.3.4 Debug Port AHB-AP interface The processor contains an Advanced High-performance Bus Access Port(AHB-AP)interface for debug accesses.An external Debug Port(DP)component accesses this interface. The Cortex-M4 system supports three possible DP implementations: an Serial Wire Debug Port (SW Th is pro es a two-pi interface to the A -AP port No DP present If no debug functionality is present within the processor,a DPisnot required. The two DP implementations provide different mechanisms for debug access to the processor.Your implementation must contain only one of these components. -Note on might for an alterative implementer-specific DP instead of SW-DPor SWJ erence manu The DP and AP together are referred to as the Debug Access Port (DAP). Related references Chapter 8 Debug on page 8-73. ARM100166_0001_00_en coapy7gne20o9,2010,2018305AdMAWngses9ned 2-26
2.3.3 AHB Trace Macrocell interface The AHB Trace Macrocell (HTM) interface enables a simple connection of the AHB trace macrocell to the processor, and provides a channel for the data trace to the HTM. Your implementation must include this interface to use the HTM interface. You must set TRCENA to 1 in the Debug Exception and Monitor Control Register (DEMCR) before you enable the HTM port to supply trace data. See the ARM® v7-M Architecture Reference Manual. 2.3.4 Debug Port AHB-AP interface The processor contains an Advanced High-performance Bus Access Port (AHB-AP) interface for debug accesses. An external Debug Port (DP) component accesses this interface. The Cortex-M4 system supports three possible DP implementations: • The Serial Wire JTAG Debug Port (SWJ-DP). The SWJ-DP is a standard CoreSight debug port that combines JTAG-DP and Serial Wire Debug Port (SW-DP). • The SW-DP. This provides a two-pin interface to the AHB-AP port. • No DP present. If no debug functionality is present within the processor, a DP is not required. The two DP implementations provide different mechanisms for debug access to the processor. Your implementation must contain only one of these components. Note Your implementation might contain an alternative implementer-specific DP instead of SW-DP or SWJDP. See your implementer for details. For more detailed information on the DP components, see the CoreSight™ Components Technical Reference manual. The DP and AP together are referred to as the Debug Access Port (DAP). For more detailed information on the debug interface, see the ARM® Debug Interface v5 Architecture Specification. Related references Chapter 8 Debug on page 8-73. 2 Functional Description 2.3 Interfaces ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 2-26 Non-Confidential
Chapter 3 Programmers'Model This chapter describes the Cortex-M4 processor programmers'model. 3.5 Write buffer on page 3-43. 3.8 Processor core register summary on page 3-47 3.9 Exceptions on page 3-49 ARM100166000100en opygh1 nghts 327
Chapter 3 Programmers’ Model This chapter describes the Cortex-M4 processor programmers’ model. It contains the following sections: • 3.1 About the programmers’ model on page 3-28. • 3.2 Modes of operation and execution on page 3-29. • 3.3 Instruction set summary on page 3-30. • 3.4 Processor memory model on page 3-40. • 3.5 Write buffer on page 3-43. • 3.6 Exclusive monitor on page 3-44. • 3.7 Bit-banding on page 3-45. • 3.8 Processor core register summary on page 3-47. • 3.9 Exceptions on page 3-49. ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 3-27 Non-Confidential
3Abot prmmrsmoe 3.1 About the programmers'model The Cortex-M4 programmers'model describes the processor's implementation-defined options. For a complete description of the programmers'model,refer to the ARMv7-MArchitecture Reference Related references ChapterSystem Control on page 4-51 Chapter5 Memory Protection Unit on page 5-57. Chapter 6 Nested Vectored Interrupt Controller on page 6-61 Chapter 7 Floating-Point Unit on page 7-65. Chapter 8 Debug on page 8-73. Chapter 9 Data Watchpoint and Trace Unit on page 9-84. Chapter 10 Instrumentation Trace Macrocell Unit on page 10-88. Chapter 11 Trace Port Interface Unit on page 11-92. ARM100166_0001_00_en capynine209,2010,20m82915AMAu7gsesened 3-28
3.1 About the programmers’ model The Cortex-M4 programmers’ model describes the processor’s implementation-defined options. For a complete description of the programmers’ model, refer to the ARM® v7-M Architecture Reference Manual, which also contains the ARMv7-M Thumb instructions the model uses, and their cycle counts for the processor. In addition, other options of the programmers’ model are described in the System Control, MPU, NVIC, FPU, Debug, DWT, ITM, and TPIU features topics. Related references Chapter 4 System Control on page 4-51. Chapter 5 Memory Protection Unit on page 5-57. Chapter 6 Nested Vectored Interrupt Controller on page 6-61. Chapter 7 Floating-Point Unit on page 7-65. Chapter 8 Debug on page 8-73. Chapter 9 Data Watchpoint and Trace Unit on page 9-84. Chapter 10 Instrumentation Trace Macrocell Unit on page 10-88. Chapter 11 Trace Port Interface Unit on page 11-92. 3 Programmers’ Model 3.1 About the programmers’ model ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 3-28 Non-Confidential
32 Modes 3.2 Modes of operation and execution The Cortex-M4 processor supports Thread and Handler operating modes,and may be run in Thumb or eggkoacaireadkooeamW See the armv7-MArchitecture reference manual for more information about these modes of operation and execution Operating modes The conditions which cause the processor to enter Thread or Handler mode are as follows: .The processor enters Thread mode on Reset,or as a result of an exception retur.Privileged and Unprivileged code can run in Thread mode. The processor enters Handler mode as a result of an exception.All code is privileged in Handler mode. Operating states The processor can operate in thumb or debug state: Thumb state.This is normal execution running 16-bit and 32-bit halfword aligned Thumb instructions. .Debug State.This is the state when the processor is in halting debug Privileged access and user access Handler mode isalways privileged.Thread mode can be privileged or unprivileged. ARM100166000100en opygh1 nghts 3-29
3.2 Modes of operation and execution The Cortex-M4 processor supports Thread and Handler operating modes, and may be run in Thumb or Debug operating states. In addition, the processor can limit or exclude access to some resources by executing code in privileged or unprivileged mode. See the ARM® v7-M Architecture Reference Manual for more information about these modes of operation and execution. Operating modes The conditions which cause the processor to enter Thread or Handler mode are as follows: • The processor enters Thread mode on Reset, or as a result of an exception return. Privileged and Unprivileged code can run in Thread mode. • The processor enters Handler mode as a result of an exception. All code is privileged in Handler mode. Operating states The processor can operate in thumb or debug state: • Thumb state. This is normal execution running 16-bit and 32-bit halfword aligned Thumb instructions. • Debug State. This is the state when the processor is in halting debug. Privileged access and user access Handler mode is always privileged. Thread mode can be privileged or unprivileged. 3 Programmers’ Model 3.2 Modes of operation and execution ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 3-29 Non-Confidential
33ane6aa 3.3 Instruction set summary The processor implements the ARMv7-M Thumb instruction set.and is binary compatible with the instruction sets and features implemented in other Cortex-M profile processors.Instructions can be paired in a way that achieves optimum reductions in timing. .3.3.2Tabe of proc 3.3.3 Load/ 3-3 ons on page 3-35. 334 Bin ary compa Cortex processors on page 3-38 3.3.1 Table of processor instructions The table su es the cortex-M4 ction set not all load and stor states. Within the assembler syntax,depending on the operation,the op>field can be replaced with one of the following options: .A simple register specifier,for example Rm. An immediate shifted register,for example Rm,LSL #4. A register shifted register,for example Rm,LSL Rs. An immediate value,for example #exEe80E000. The following abbreviations are used in the Cycles column: The number d for the address early. B The of n the For DSB the mini N The number of registers in the register list to be loaded or stored,including PC or LR The number of cycles spent waiting for an appropriate event. Table 3-1 Processor instruction set summary Operation Description Assembler Cycles Notes Move Register MOV Rd,<op2> 1 16-bit immediate MOVW Rd,#imm> 1 Immediate into top MOVT Rd,#imm> 1 To PC MOV PC,Rm 1+P ARM100166_0001_00_en Copygh1gsve 3-30 Non-Cor
3.3 Instruction set summary The processor implements the ARMv7-M Thumb instruction set, and is binary compatible with the instruction sets and features implemented in other Cortex-M profile processors. Instructions can be paired in a way that achieves optimum reductions in timing. This section contains the following subsections: • 3.3.1 Table of processor instructions on page 3-30. • 3.3.2 Table of processor DSP instructions on page 3-35. • 3.3.3 Load/store timings on page 3-37. • 3.3.4 Binary compatibility with other Cortex processors on page 3-38. 3.3.1 Table of processor instructions The table summarizes the Cortex-M4 processor instruction set. For brevity, not all load and store addressing modes are shown in the table. The cycle counts provided are based on a system with zero wait states. Within the assembler syntax, depending on the operation, the <op2> field can be replaced with one of the following options: • A simple register specifier, for example Rm. • An immediate shifted register, for example Rm, LSL #4. • A register shifted register, for example Rm, LSL Rs. • An immediate value, for example #0xE000E000. For brevity, not all load and store addressing modes are shown. See the ARMv7-M Architecture Reference Manual for more information. The following abbreviations are used in the Cycles column: P The number of cycles required for a pipeline refill. This ranges from 1 to 3 depending on the alignment and width of the target instruction, and whether the processor manages to speculate the address early. B The number of cycles required to perform the barrier operation. For DSB and DMB, the minimum number of cycles is zero. For ISB, the minimum number of cycles is equivalent to the number required for a pipeline refill. N The number of registers in the register list to be loaded or stored, including PC or LR. W The number of cycles spent waiting for an appropriate event. Table 3-1 Processor instruction set summary Operation Description Assembler Cycles Notes Move Register MOV Rd, <op2> 1 16-bit immediate MOVW Rd, #<imm> 1 Immediate into top MOVT Rd, #<imm> 1 To PC MOV PC, Rm 1 + P 3 Programmers’ Model 3.3 Instruction set summary ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 3-30 Non-Confidential