Altera Corporation SDR SDRAM Controller White Paper Figure 3. WRITEA Timing Diagram CKE WRJTEA X NOP CMDACK DATAINDc I IX 5x6x7x ax p.c. Ⅸ X XXX p.c. RAS N CAS N DOM Ⅸ XXXX D.C.= Don't Care REFRESH Command The REFRESH command instructs the SDR SDRAM Controller to perform an ARF command to the SDram. The SDR SDRAM Controller acknowledges the REFRESH command with CMDACK. Figure 4 shows an example timing diagram of the REFRESH command. The following sequence describes the general operation of a REFRESH com- mand The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu- ing commands to the sdram devices The user asserts NoP on CMD
Altera Corporation SDR SDRAM Controller White Paper 6 Figure 3. WRITEA Timing Diagram REFRESH Command The REFRESH command instructs the SDR SDRAM Controller to perform an ARF command to the SDRAM. The SDR SDRAM Controller acknowledges the REFRESH command with CMDACK. Figure 4 shows an example timing diagram of the REFRESH command. The following sequence describes the general operation of a REFRESH command: ■ The user asserts REFRESH on the CMD input ■ The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issuing commands to the SDRAM devices ■ The user asserts NOP on CMD Address 1234567 Row Column CLK CMD CMDACK ADDR DATAIN DQM RAS_N CAS_N WE_N DQ SA BA CS_N CKE WRITEA NOP 1 2345678 DM D.C. = Don't Care NOP D.C. D.C. D.C. D.C. D.C. D.C. 8
Altera Corporation SDR SDRAM Controller White Paper Figure 4. REFRESH Timing Diagram CMD EFRESH CMDACK RAS N CAS N PRECHARGE Command The PRECHARGE command instructs the SDR SDRAM Controller to perform a PCH command to the SDram The SDR SDRAM Controller acknowledges the command with CMDACK. The PCH command is also used to gener ate a burst stop to the SDRAM. Using PRECHARGe to terminate a burst is only supported in the full-page mode Note that the SDR SDRAM Controller adds a latency from when the host issues a command to when the SDraM sees the PRECHaRGE command of 4 clocks. If a full-page read burst is to be stopped after 100 cycles, the PRE- CHARGE command must be asserted (4+Cl-1)clocks before the desired end of the burst(CL-I requirement imposed by the SDRaM devices). So if the CAs latency is 3, the PRECHARGE command must be issued (100-3 1-4)=92 clocks into the burst Figure 5 shows an example timing diagram of the PRECHARGE command. The following sequence describes the general operation of a PRECHARGE command The user asserts PRECharGe on CMI The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu- ing commands to the sdram devices The user asserts NoP on CMD
Altera Corporation SDR SDRAM Controller White Paper 7 Figure 4. REFRESH Timing Diagram PRECHARGE Command The PRECHARGE command instructs the SDR SDRAM Controller to perform a PCH command to the SDRAM. The SDR SDRAM Controller acknowledges the command with CMDACK. The PCH command is also used to generate a burst stop to the SDRAM. Using PRECHARGE to terminate a burst is only supported in the full-page mode. Note that the SDR SDRAM Controller adds a latency from when the host issues a command to when the SDRAM sees the PRECHARGE command of 4 clocks. If a full-page read burst is to be stopped after 100 cycles, the PRECHARGE command must be asserted (4 + CL – 1) clocks before the desired end of the burst (CL – 1 requirement is imposed by the SDRAM devices). So if the CAS latency is 3, the PRECHARGE command must be issued (100 – 3 – 1 – 4) = 92 clocks into the burst. Figure 5 shows an example timing diagram of the PRECHARGE command. The following sequence describes the general operation of a PRECHARGE command: ■ The user asserts PRECHARGE on CMD ■ The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issuing commands to the SDRAM devices ■ The user asserts NOP on CMD CLK CMD CMDACK DQM RAS_N CAS_N WE_N DQ SA BA CS_N CKE REFRESH NOP CLK FREQ = 133 MHz NOP