高级计算机体系结构设计及其在数据中心和云计算的应用Coherence with Write-through Caches. Allows multiple readers, but writes through to bus- Requires Write-through, no-write-allocate cacheAll caches must monitor (aka“snoop")all bus traffic-SimplestatemachineforeachcacheframeP2P1t1: Store A=1A[V]:01A[VI]:0Write-throught3:InvalidateANo-write-allocateBust2: BusWr A=1A: 01MainMemory
高级计算机体系结构设计及其在数据中心和云计算的应用 Coherence with Write-through Caches • Allows multiple readers, but writes through to bus – Requires Write-through, no-write-allocate cache • All caches must monitor (aka “snoop”) all bus traffic – Simple state machine for each cache frame P1 t1: Store A=1 P2 Bus A: 0 A [V]: 0 A [V]: 0 Main Memory Write-through No-write-allocate t2: BusWr A=1 A [V I]: 0 t3: Invalidate A A: 0 1 A [V]: 0 1
高级计算机体系结构设计及其在数据中心和云计算的应用Valid-Invalid Snooping ProtocolProcessorActions- Ld, St, BusRd, BusWrLoad / --Store/BusWrBus Messages-BusRd,BusWrValidTrack1bitpercacheframeBusWr/---Valid/InvalidLoad / BusRdInvalidStore/BusWr
高级计算机体系结构设计及其在数据中心和云计算的应用 Valid-Invalid Snooping Protocol • Processor Actions – Ld, St, BusRd, BusWr • Bus Messages – BusRd, BusWr • Track 1 bit per cache frame Store / BusWr Load / - Valid • Track 1 bit per cache frame – Valid/Invalid BusWr / - Store / BusWr Load / BusRd Invalid
高级计算机体系结构设计及其在数据中心和云计算的应用Supporting Write-Back Caches.Write-back caches are good-DrasticallyreducebuswritebandwidthAdd notionof“ownership"to Valid-lnvalid-When“owner"hasonlyreplicaofacacheblock.Updateit freely-Multiplereadersareok.Not allowed to write withoutgaining ownership-Onaread,systemmust check if thereisanowner.Ifyes,takeawayownership
高级计算机体系结构设计及其在数据中心和云计算的应用 Supporting Write-Back Caches • Write-back caches are good – Drastically reduce bus write bandwidth • Add notion of “ownership” to Valid-Invalid – When “owner” has only replica of a cache block • Update it freely – Multiple readers are ok • Not allowed to write without gaining ownership – On a read, system must check if there is an owner • If yes, take away ownership
高级计算机体系结构设计及其在数据中心和云计算的应用Modified-Shared-lnvalid (MSl) StatesProcessorActions-Load,Store,EvictBusMessages-BusRd,BusRdX,Buslnv,BusWB,BusReply(Here for simplicity, some messages can be combined)Track 3 statesper cacheframe- Invalid: cache does not have a copy-Shared:cache hasa read-onlycopy;clean:Clean:memory (orlater caches)is upto date-Modified:cache has the only valid copy; writable; dirty: Dirty: memory (or later caches) is out of date
高级计算机体系结构设计及其在数据中心和云计算的应用 Modified-Shared-Invalid (MSI) States • Processor Actions – Load, Store, Evict • Bus Messages – BusRd, BusRdX, BusInv, BusWB, BusReply (Here for simplicity, some messages can be combined) • Track 3 states per cache frame – Invalid: cache does not have a copy – Shared: cache has a read-only copy; clean • Clean: memory (or later caches) is up to date – Modified: cache has the only valid copy; writable; dirty • Dirty: memory (or later caches) is out of date