SRAM (Static Random Access Memory)ReadSequencerow select1. address decode2.drive row select3.selectedbit-cellsdrivebitlinesn(entire row is read together)4. differential sensing and column select(data is ready)5.precharge all bitlines(for next read or write)bit-cell array2nn+mnAccess latencydominated bysteps2 and 32nrowx2m-colCyclingtimedominatedbysteps2,3and5(n-mto minimize:step2proportionalto2moverall latency):step3and5proportional to2nm+2mdiffpairssenseampandmux1ComputerArchitecture11
Computer Architecture SRAM (Static Random Access Memory) 11 bit-cell array 2n row x 2m-col (n≈m to minimize overall latency) sense amp and mux 2m diff pairs 2n n m 1 row select bitline _bitline n+m Read Sequence 1. address decode 2. drive row select 3. selected bit-cells drive bitlines (entire row is read together) 4. differential sensing and column select (data is ready) 5. precharge all bitlines (for next read or write) Access latency dominated by steps 2 and 3 Cycling time dominated by steps 2, 3 and 5 - step 2 proportional to 2m - step 3 and 5 proportional to 2n
DRAM (Dynamic Random Access Memory)Bits storedascharges onnoderowenablecapacitance(non-restorative).bitcell loseschargewhenread.bit cell loses charge overtimeReadSequenceV1~3 same as SRAM4.a“flip-flopping"senseampRASbit-cell arrayamplifies and regenerates thebitline,databitismux'ed out2nn2nrowx2m-col5. precharge all bitlines(n~mtominimizeDestructive readsoverall latency)ChargelossovertimeRefresh:ADRAMcontrollermust+2mmsenseampandmuxperiodicallyread eachrowwithinthe#1allowedrefreshtime(10sofms)suchADRAMdiecomprisesthat charge is restoredofmultiplesucharraysCASComputerArchitecture12
Computer Architecture DRAM (Dynamic Random Access Memory) 12 row enable _bitline bit-cell array 2n row x 2m-col (n≈m to minimize overall latency) sense amp and mux 2m 2n n m 1 RAS CAS A DRAM die comprises of mul4ple such arrays Bits stored as charges on node capacitance (non-restorative) - bit cell loses charge when read - bit cell loses charge over time Read Sequence 1~3 same as SRAM 4. a “flip-flopping” sense amp amplifies and regenerates the bitline, data bit is mux’ed out 5. precharge all bitlines Destructive reads Charge loss over time Refresh: A DRAM controller must periodically read each row within the allowed refresh time (10s of ms) such that charge is restored
DRAM VS. SRAM·DRAM- Slower access (capacitor)- Higher density (1T 1C cell)- Lower cost- Requires refresh (power, performance, circuitry)- Manufacturing requires putting capacitor and logic together·SRAM- Faster access (no capacitor)- Lower density (6T cell)- Higher cost- No need for refreshManufacturing compatiblewith logicprocess (no capacitor)Computer Architecture13
Computer Architecture DRAM vs. SRAM • DRAM – Slower access (capacitor) – Higher density (1T 1C cell) – Lower cost – Requires refresh (power, performance, circuitry) – Manufacturing requires putting capacitor and logic together • SRAM – Faster access (no capacitor) – Lower density (6T cell) – Higher cost – No need for refresh – Manufacturing compatible with logic process (no capacitor) 13
The Problem· Bigger is slower- SRAM, 512 Bytes, sub-nanosec- SRAM,KByte~MByte,~nanosec- DRAM,Gigabyte, ~50 nanosec- Hard Disk, Terabyte, ~10 millisecFaster is more expensive (dollars and chip area)- SRAM, < 10$ per Megabyte- DRAM, < 1$ per Megabyte- Hard Disk < 1$ per Gigabyte- These sample values scale with time: Other technologies have their place as well- Flash memory, Phase-change memory (not mature yet)ComputerArchitecture14
Computer Architecture The Problem • Bigger is slower – SRAM, 512 Bytes, sub-nanosec – SRAM, KByte~MByte, ~nanosec – DRAM, Gigabyte, ~50 nanosec – Hard Disk, Terabyte, ~10 millisec • Faster is more expensive (dollars and chip area) – SRAM, < 10$ per Megabyte – DRAM, < 1$ per Megabyte – Hard Disk < 1$ per Gigabyte – These sample values scale with time • Other technologies have their place as well – Flash memory, Phase-change memory (not mature yet) 14
Why MemoryHierarchy?. We want both fast and large But we cannot achieve both with a single level ofmemory Idea: Have multiple levels of storage (progressivelybigger and slower as the levels are farther fromthe processor) and ensure most of the data theprocessor needs is kept in the fast(er) level(s)ComputerArchitecture15
Computer Architecture Why Memory Hierarchy? • We want both fast and large • But we cannot achieve both with a single level of memory • Idea: Have multiple levels of storage (progressively bigger and slower as the levels are farther from the processor) and ensure most of the data the processor needs is kept in the fast(er) level(s) 15