Ideal Memory: Zero access time (latency).Infinite capacity?Zero cost: Infinite bandwidth (to support multiple accesses inparallel)ComputerArchitecture
Computer Architecture Ideal Memory • Zero access time (latency) • Infinite capacity • Zero cost • Infinite bandwidth (to support multiple accesses in parallel) 6
The Problem: Ideal memory's requirements oppose each other·Bigger is slower- Bigger →> Takes longer to determine the location.Faster is more expensive- Memory technology: SRAM vs. DRAM.Higher bandwidth is more expensiveNeed more banks, more ports, higher frequency, orfaster technologyComputerArchitecture
Computer Architecture The Problem • Ideal memory’s requirements oppose each other • Bigger is slower – Bigger à Takes longer to determine the location • Faster is more expensive – Memory technology: SRAM vs. DRAM • Higher bandwidth is more expensive – Need more banks, more ports, higher frequency, or faster technology 7
Memory Technology: DRAM: Dynamic random access memory: Capacitor charge state indicates stored value- Whether the capacitor is charged or discharged indicatesstorage of 1 or 0- 1 capacitor- 1 access transistorrowenable Capacitor leaks through the RC pathue- DRAM cell loses charge over time- DRAM cell needs to be refreshedComputerArchitecture
Computer Architecture Memory Technology: DRAM • Dynamic random access memory • Capacitor charge state indicates stored value – Whether the capacitor is charged or discharged indicates storage of 1 or 0 – 1 capacitor – 1 access transistor • Capacitor leaks through the RC path – DRAM cell loses charge over time – DRAM cell needs to be refreshed 8 row enable _ bitline
Memory Technology: SRAM: Static random access memory. Two cross coupled inverters store a single bit- Feedback path enables the stored value to persist in the"cell"- 4transistors for storage- 2 transistors for accessrowselectuennComputerArchitecture
Computer Architecture • Static random access memory • Two cross coupled inverters store a single bit – Feedback path enables the stored value to persist in the “cell” – 4 transistors for storage – 2 transistors for access Memory Technology: SRAM 9 row select bitline _ bitline
Memory Bank Organization and OperationReadaccesssequence:2DStorage1.Decoderowaddress&driveword-linesArrayerMSbits2.Selectedbitsdrivebit-lines.Entire row read3.Amplify row data4. Decode columnLSbitsColumnDecoderaddress&selectsubsetof row.Send to outputData Out5.Prechargebit-lines·FornextaccessComputerArchitecture10
Computer Architecture Memory Bank Organization and Operation • Read access sequence: 1. Decode row address & drive word-lines 2. Selected bits drive bit-lines • Entire row read 3. Amplify row data 4. Decode column address & select subset of row • Send to output 5. Precharge bit-lines • For next access 10