2器时 10.2速度优化 10.21流水线设计 未使用 流水线 信号1 信号1 流水线信号1信号2 第1级 流水线 信号1信号2 第2级 图10-8流水线工作图示
康芯科技 10.2 速度优化 10.2.1 流水线设计 信号1 信号2 信号1 信号2 信号1 信号1 未使用 流水线 流水线 第1级 流水线 第2级 图10-8 流水线工作图示
2器时 【例10-7】 LIBRARY ieee: USE ieee std logic 1164.all; use ieee std logic unsigned. all: use ieee std logic arith all ENTITY adder is PORT(clk in std logic; 10, a1 a2 a3: in std logic vector( 7 downto 0); yout out std logic vector( 9 downto 0)); END adder: ARCHITECtURE normal arch of adder Is signal to, tl, t2, t3: std logic vector(7 downto 0); signal addtmp0, addtmpl std logic vector(8 downto 0) BEGIN process(clk begin if(clk'event and clke'l)then t0<=a0;t<=al;t2<=a2;t3<=a3: end if: addtmp0<=0&t0+ tI addtmpl <='0'&t2+ t3; process(clk) begin if(clk'event and clk='1) then yout <=0&addtmp0 addtmpl; end if: end proces END normal arc h
康芯科技 【例10-7】 LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY adder4 IS PORT(clk : in std_logic; a0,a1,a2,a3 : in std_logic_vector(7 downto 0); yout : out std_logic_vector(9 downto 0)); END adder4; ARCHITECTURE normal_arch OF adder4 IS signal t0,t1,t2,t3 : std_logic_vector(7 downto 0); signal addtmp0,addtmp1 : std_logic_vector(8 downto 0); BEGIN process(clk) begin if(clk'event and clk='1') then t0 <= a0; t1 <= a1; t2 <= a2; t3 <= a3; end if; end process; addtmp0 <= '0'&t0 + t1; addtmp1 <= '0'&t2 + t3; process(clk) begin if(clk'event and clk = '1') then yout <= '0'&addtmp0 + addtmp1; end if; end process; END normal_arch;
【例10-8】 2器时 LIBRARY ieee; USE ieee std logic 1164. all; use ieeestd logic unsigned. all; use ieee std logic arith.all ENTITY pipeadd Is PORT(clk in std logic a0, a1, a2, a3: in std logic vector(7 downto 0) yout: out std logic vector(9 downto 0)); END pipeadd; ARCHITECTURE Pipe lining arch oF pipeadd is signal to, tl, t 2, t3: std logic vector(7 downto 0); A signal addtmp, addtmpl: std logic vector( 8 downto 0); BEGIN process(clk) begin if(clk'event and clk1") then t0<=a0;t<=al;t<=a2;t3<a3; end if: end process; process(clk) begin if(clk'event and clk=1")then addtmp0 <=0&t0+ tI addtmpl <=0&t2+ t3; yout <=0&addtmp0 addtmpl; en nd process END pipe lining arch
康芯科技 【例10-8】 LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY pipeadd IS PORT(clk : in std_logic; a0,a1,a2,a3 : in std_logic_vector(7 downto 0); yout : out std_logic_vector(9 downto 0)); END pipeadd; ARCHITECTURE pipelining_arch OF pipeadd IS signal t0,t1,t2,t3 : std_logic_vector(7 downto 0); signal addtmp0,addtmp1 : std_logic_vector(8 downto 0); BEGIN process(clk) begin if(clk'event and clk='1') then t0 <= a0; t1 <= a1; t2 <= a2; t3 <= a3; end if; end process; process(clk) begin if(clk'event and clk = '1') then addtmp0 <= '0'&t0 + t1; addtmp1 <= '0'&t2 + t3; yout <= '0'&addtmp0 + addtmp1; end if; end process; END pipelining_arch;
2器时 10.2速度优化 1022寄存器配平 T2 T1>T2 D9组合逻辑 延时较小 组合逻辑2 少触发器 少触发器 少触发器 clk 图10-9不合理的结构
康芯科技 10.2 速度优化 10.2.2 寄存器配平 图10-9 不合理的结构 延时较大 （组合逻辑1） Q Q SET CLR D 触发器 Q Q SET CLR D 触发器 clk Q Q SET CLR D 触发器 延时较小 （组合逻辑2） T1 T2 T1＞T2 T1 T1>T2 T2 Q Q Q Q Q Q
2器时 10.2速度优化 1022寄存器配平 t1≈t2 t2 延时块 延时块 (组合逻辑1 (组合逻辑2 触发器 少>触发器 少触发器 CLR clk 图10-10寄存器配平的结构
康芯科技 10.2 速度优化 10.2.2 寄存器配平 图10-10 寄存器配平的结构 延时块 （组合逻辑1） Q Q SET CLR D 触发器 Q Q SET CLR D 触发器 clk Q Q SET CLR D 触发器 延时块 （组合逻辑2） t1t1 t1≈t2 t1≈t2 t2t2 Q Q Q Q Q Q