【例10-6】 2器时 LIBRARY ieee USE ieee std logic 1164.all: use ieee std logic unsigned. all use ieee std logic arith. all; ENTITY Smultadd is PORT(clk, start: in std logic a0, a1, a2, a3: In std logic vector(7 downto 0); b0, b1, b2, b3: In std logic vector(7 downto 0); yout: out std logic vector(15 downto O)); END Smultadds ARCHITECTURE s arch of smultadd Is signal cnt: std logic vector(2 downto 0) signal tmpa, tmpb: std logic vector(7 downto 0); signal tmp, tmp: std logic vector(15 downto 0); BEGIN tmpa <=a0 when cnt=0 else al when cnt=l else a2 when cnt=2 else a3 when cnt=3 else 接下页 a0;
康芯科技 【例10-6】 LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY smultadd IS PORT(clk，start: in std_logic; a0,a1,a2,a3 : In std_logic_vector(7 downto 0); b0,b1,b2,b3 : In std_logic_vector(7 downto 0); yout : out std_logic_vector(15downto 0)); END smultadd; ARCHITECTUREs_archOF smultadd IS signal cnt : std_logic_vector(2downto 0); signal tmpa，tmpb : std_logic_vector(7 downto 0); signal tmp， ytmp : std_logic_vector(15downto 0); BEGIN tmpa <= a0 when cnt = 0 else a1 when cnt = 1 else a2 when cnt = 2 else a3 when cnt = 3 else a0; 接下页
2器时 tmpb < bo when cnt=0 else bI when cnt=l else b2 when cnt=2 else b3 when cnt=3 else bO: tmp<=tmpa* tmpb process(clk) begin if(clk'event and clk=1)then if(start='1)then cnt <=000;tmp <=(others=>0); elsif(cnt<4 ) then cnt <=cnt+ 1; ytmp<= ytmp tmp elsif(cnt=4)then yout <=ytmp end if end if: end process; ENDS arch
康芯科技 tmpb <= b0 when cnt = 0 else b1 when cnt = 1 else b2 when cnt = 2 else b3 when cnt = 3 else b0; tmp <= tmpa * tmpb; process(clk) begin if(clk'event and clk = '1') then if(start = '1')then cnt <= "000"; ytmp <= (others=>'0'); elsif (cnt<4) then cnt <= cnt + 1; ytmp <= ytmp + tmp; elsif (cnt = 4) then yout <= ytmp; end if; end if; end process; END s_arch;
10.13串行化 2器时 D[150] C15.01 15q150yor0> > 图10-5串行化结构
康芯科技 10.1.3 串行化 图10-5 串行化结构 [15:0] Q[15:0] [1:16] D[15:0] R E + [15:0] [1:16] [15:0] * [7:0] [15:0] [7:0] [2:0] Q[2:0] [2:0] D[2:0] e d e d e d e d [7:0] [7:0] [7:0] [7:0] [7:0] e d e d e d e d [7:0] [7:0] [7:0] [7:0] [7:0] 0 1 [0:2] [2:0] 000 [15:0] Q[15:0] [15:0] D[15:0] E + [2:0] [0:2] [2] [0] [1] [0] [1] [2] [1] [0] [0] [1] [0] [1] yout[15:0] [15:0] b3[7:0] [7:0] b2[7:0] [7:0] b1[7:0] [7:0] b0[7:0] [7:0] a3[7:0] [7:0] a2[7:0] [7:0] a1[7:0] [7:0] a0[7:0] [7:0] start clk
2器时 102速度优化 1021流水线设计 延时较大的 D 组合逻辑块 >触发器 少触发器 CLR clk 图10-6未使用流水线
康芯科技 10.2 速度优化 10.2.1 流水线设计 图10-6 未使用流水线 延时较大的 组合逻辑块 Ta Q Q SET CLR D 触发器 Q Q SET CLR D 触发器 clk
2器时 10.2速度优化 102.1流水线设计 Ta =l+ T 延时较小的 延时较小的 Dax组合逻辑块 组合逻辑块 触发器 少触发器 触发器 clk 图10-7使用流水线
康芯科技 10.2 速度优化 10.2.1 流水线设计 图10-7 使用流水线 延时较小的 组合逻辑块 T1 Q Q SET CLR D 触发器 Q Q SET CLR D 触发器 clk Q Q SET CLR D 触发器 延时较小的 组合逻辑块 T2 Ta = T1 + T2