EDA技术实用教程 第8章 VHDL结构与要素
第8章 VHDL结构与要素 EDA技术实用教程
K述列 8.1实体 8.1.1实体语句结构 ENTTY实体名rs [ GENERIC(类属表); [PORT(端口表);] END EN乎TY实体名; 81.2 GENERIC类属说明语句 GENERIC([常数名:数据类型[:设定值 【;常数名:数据类型[:设定值]})
KX 康芯科技 8.1 实 体 8.1.1 实体语句结构 ENTITY 实体名 IS [GENERIC ( 类属表 );] [PORT ( 端口表 );] END ENTITY 实体名; 8.1.2 GENERIC类属说明语句 GENERIC([ 常数名 : 数据类型 [ : 设定值 ] { ;常数名 : 数据类型 [ : 设定值 ] } ) ;
例8-1】 LIBRARY IEEE: USE IEEE STD LOGIC 1164.ALL ENTITY andn Is GENERIO(n: INTEGER);-定义类属参量及其数据类型 PORT(a: IN STD LOGIOⅤ ECTOR(n-1 DOWNTO0;-用类属参量限制矢 量长度 C: OUT STD LOGIC); END: architecture belay of andn is BEGIN PROCESS(a) VaRIABLE int: STD LOGIC: BEGIN int: =1 FORiin a'lENgTH-1 doWNton LOOP IFa()=0 then int: =0 END IF END LOOP c <=int END PROCESS: END:
KX 【例8-1】 康芯科技 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY andn IS GENERIC ( n : INTEGER ); --定义类属参量及其数据类型 PORT(a : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);--用类属参量限制矢 量长度 c : OUT STD_LOGIC); END; ARCHITECTUREbehav OF andn IS BEGIN PROCESS (a) VARIABLE int : STD_LOGIC; BEGIN int := '1'; FOR i IN a'LENGTH- 1 DOWNTO0 LOOP IF a(i)='0'THEN int := '0'; END IF; END LOOP; c <=int ; END PROCESS; END;
K述列 【例82】 LIBRARY IEEE USE IEEE STD LOGIC 1164.ALL ENTITY exn is PORT(dl, d2, d3, d4, d5, d6, d7: IN STD LOGIC; ql, q2: OUTSTD LOGIC); END ARCHITECTURE exn behav of exn Is COMPONENT andn 元件调用声明 GENERIC(n: INTEGER) PORT(a: IN STD LOGIC VECTOR(n-1 DOWNTOO C: OUT STD LOGIC); END COMPONENT; BEGIN-类属映射语句,定义类属变量,n赋值为2 ul: andn genErIC MaP (n=>2) PORT MAP (a(0=>dl, a(1=>d2, c=>q1); u2: andn GENERIc map(n→>5)-定义类属变量,m赋值为5 PORT MAP(a(0)=>d3,a(1)→>d4,a(2)→>d5 a(3)→>d6,a(4)→>d7,c→>q2); END
KX 康芯科技 【例8-2】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY exn IS PORT(d1,d2,d3,d4,d5,d6,d7 : IN STD_LOGIC; q1,q2 : OUT STD_LOGIC); END; ARCHITECTUREexn_behav OF exn IS COMPONENTandn --元件调用声明 GENERIC ( n : INTEGER); PORT(a : IN STD_LOGIC_VECTOR(n-1 DOWNTO0); C : OUT STD_LOGIC); END COMPONENT; BEGIN -- 类属映射语句，定义类属变量，n赋值为2 u1: andn GENERIC MAP (n =>2) PORTMAP (a(0)=>d1,a(1)=>d2,c=>q1); u2: andn GENERIC MAP (n =>5) -- 定义类属变量，n赋值为5 PORT MAP (a(0)=>d3,a(1)=>d4,a(2)=>d5, a(3)=>d6,a(4)=>d7, c=>q2); END;
K述列 8.1实体 8.1.3类属映射语句 【例8-3】 LIBRARY IEEE: 待例化元件 USE IEEE STD LOGIC 1164.ALL: USE IEEE STD LOGIC arithALL USE IEEE STD LOGIC unsigned.ALL ENTITY addern s PORT(a, b: IN STD LOGIC VECTOR: result: out STD LOGIC VECTOR) END addern; architecture be have of addern Is BEGIN result < a+ by END:
KX 康芯科技 8.1.3 类属映射语句 8.1 实 体 【例8-3】 LIBRARY IEEE; --待例化元件 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY addern IS PORT (a, b: IN STD_LOGIC_VECTOR; result: out STD_LOGIC_VECTOR); END addern; ARCHITECTURE behave OF addern IS BEGIN result <= a + b; END;