2器时 112 Synplify与MAX+pus的接口 2.选择合适的目标器件 3.综合前控制设置 4.综合 5.结果检测
康芯科技 3. 综合前控制设置 4. 综合 5. 结果检测 2. 选择合适的目标器件 11.2 Synplify与MAX+plusII的接口
2器时 【例11-1】 library ieee use ieee std logic 1164.alli use ieee std logic unsigned alli entity cnt4 is port (d: in std logic vector (3 downto 0)i ld, ce, clk, rst in std logici g: out std logic vector (3 downto o))i end cnt4 archi tecture behave of cnt4 is signal count std logic vector (3 downto o)i begin process (clk, rst begin if rst=l then count <=(others =>0)i elsif rising edge(clk)then if ld =1 then count < elsif ce 'l then count < count l end ifi end if; end processi g < counti end behave
康芯科技 【例11-1】 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt4 is port (d : in std_logic_vector (3 downto 0); ld, ce, clk, rst : in std_logic; q : out std_logic_vector (3 downto 0)); end cnt4; architecture behave of cnt4 is signal count : std_logic_vector (3 downto 0); begin process (clk, rst) begin if rst = '1' then count <= (others => '0'); elsif rising_edge(clk) then if ld = '1' then count <= d; elsif ce = '1' then count <= count + 1; end if; end if; end process; q <= count; end behave;
2器时 112 Synplify与MAX十pus的接口 4 Sheet 1 of 1- top level (of module ent4)(RTL Vier)Inpl-rev_ +o Instances (3) +o Nets (8) 10-B0D(3. 0 Q(3: 0) Had 80 Q(3:0 un1q4:1] [d[3: 0 count 4[3:0 q[30] 图114 Synplify的RTL级原理图
康芯科技 图11-4 Synplify的RTL 级原理图 11.2 Synplify与MAX+plusII的接口
2器时 12 ynplify与MAX+plu的接口 Sheet 1 of 1- top level (of module cnt4) (Technology Vier) AT000: EPI7032LC44-7 Impl-rey 1 +o Instances (18) rst +o Ports(6) +o Nets (20) SDFFE d[3:0]- CLK q no d ENA qlO 图115 Synplify的综合后门级电路图
康芯科技 11.2 Synplify与MAX+plusII的接口 图11-5 Synplify的综合后门级电路图
2器时 112 Synplify与MAX+plu的接口 6.设定EDF文件为工程 EDIF netlist Reader Settings Vendor:Synplicity 厂 Show LMF Mapping Messages 7.选定EDF文件来源 Customize > OK Cancel 8.选定目标器件 Signal Names VCC: CC GND: GND 9.编译适配 Library Mapping Files F LMF #1C e: \edapro\maxplus 2\lmf\ synplctyImf T LMF #2C e: \edapro'ksynp62 \synplify (lib \synplcty Imf Directory is: e: \edapro\synp 62\synplifywytmp \rev_3 Directories 图116 Synplify的 综合后门级电路图 Drives
康芯科技 11.2 Synplify与MAX+plusII的接口 6. 设定EDF文件为工程 7. 选定EDF文件来源 图11-6 Synplify的 综合后门级电路图 8. 选定目标器件 9. 编译适配