高级计算机体系结构设计及其在数据中心和云计算的应用Memory Organization (2/3)ProcessorCore0Core IRegistersRegistersD-TLB1-TLBLI D-CacheI-TLBLI D-CacheD-TLBLII-CacheLII-CacheL2CacheL2CacheL3Cache (LLC)Main Memory (DRAM)Multi-corereplicatesthetop ofthehierarchy
高级计算机体系结构设计及其在数据中心和云计算的应 用 Processor Memory Organization (2/3) Main Memory (DRAM) L3 Cache (LLC) Core 0 Registers L1 I-Cache L1 D-Cache L2 Cache I-TLB D-TLB Core 1 Registers L1 I-Cache L1 D-Cache L2 Cache I-TLB D-TLB Multi-core replicates the top of the hierarchy
高级计算机体系结构设计及其在数据中心和云计算的应用Memory Organization (3/3)er(ese)NS9HSO2CoreCoreCoreCore2QueuTOOPH256KSharedL3Cache
高级计算机体系结构设计及其在数据中心和云计算的应 用 Memory Organization (3/3) 256K L2 32K L1-D 32K L1-I Intel Nehalem (3.3GHz, 4 cores, 2 threads per core)
高级计算机体系结构设计及其在数据中心和云计算的应用SRAMOverview0“6TSRAM"cellb2 access gates2T per inverterChainedinvertersmaintainastable stateAccess gates provide access to the cellWriting to cell involves over-powering storage inverters
高级计算机体系结构设计及其在数据中心和云计算的应 用 SRAM Overview • Chained inverters maintain a stable state • Access gates provide access to the cell • Writing to cell involves over-powering storage inverters 01 01 1 1 b b “6T SRAM” cell 2 access gates 2T per inverter
高级计算机体系结构设计及其在数据中心和云计算的应用8-bit SRAM Arraywordlinebitlines
高级计算机体系结构设计及其在数据中心和云计算的应 用 8-bit SRAM Array wordline bitlines
高级计算机体系结构设计及其在数据中心和云计算的应用Fully-AssociativeCacheKeepblocksincacheframes0:i63address- data state (e.g., valid)tag[63:6]block offset[5:0]-addresstaqstatedata三tag00datastatetagdatastatetag=datastatetagmultiplexorhit?What happens when the cache runs out of space?
高级计算机体系结构设计及其在数据中心和云计算的应 用 = = = • Keep blocks in cache frames – data – state (e.g., valid) – address tag data data data data Fully-Associative Cache multiplexor tag[63:6] block offset[5:0] address What happens when the cache runs out of space? tag tag tag tag state state state state = 63 0 hit?