Drawbacks of this approach are the loss of bandwidth as Rx works against Cl, the loss of voltage swing, a possible lower slew rate limit due to IMAX and Cl, and a gain error due to the Rx- RL division. The gain error can be optionally compensated with riN, which is ratioed to RF as Rl is to Rx. In this example, a+100mA output from the op amp into CLcan slew VouT at a rate of 100V/us, far below the intrinsic AD811 slew rate of 2500V/us. Although the drawbacks are serious, this form of cap load compensation is nevertheless useful because of its simplicity. If the amplifier not otherwise protected, then an Rx resistor of 50-100ohms should be used with virtually any amplifier facing capacitive loading. Although a non-inverting amplifier is shown, the technique is equally applicable to inverter stages With very speed high amplifiers, or in applications where lowest settling time is critical, even small values of load capacitance can be disruptive to frequency response, but are nevertheless sometimes inescapable. One case in point is an amplifier used for driving ADC inputs Since high speed ADC inputs quite often look capacitive in nature, this presents an oil/water type problem. In such cases the amplifier must be stable driving the capacitance, but it must also preserve its best bandwidth and settling time characteristics. To address this type of cap load case performance, Rs and Cl data for a specified settling time is most appropriate Some applications, in particular those that require driving the relatively high impedance of an ADC, do not have a convenient back termination resistor to dampen the effects of capacitive loading. At high frequencies, an amplifiers output impedance is rising with frequency and acts like an inductance, which in combination with Cl causes peaking or even worse, oscillation When the bandwidth of an amplifier is an appreciable percentage of device ft the situation is complicated by the fact that the loading effects are reflected back into its internal stages. In spite of this, the basic behavior of most very wide bandwidth amplifiers such as the AD8001 is very simila In general, a small damping resistor(Rs) placed in series with Cl will help restore the desired response(see Figure 2.4). The best choice for this resistors value will depend upon the criterion used in determining the desired response. Traditionally simply stability or an acceptable amount of peaking has been used, but a more strict measure such as0. 1%(or even 0.01%)settling will yield different values For a given amplifier, a family of rs-CL curves exists, such as those of Figure 2.4. These data will aid in selecting Rs for a given application
6 Drawbacks of this approach are the loss of bandwidth as RX works against CL, the loss of voltage swing, a possible lower slew rate limit due to IMAX and CL, and a gain error due to the RX-RL division. The gain error can be optionally compensated with RIN, which is ratioed to RF as RL is to RX. In this example, a ±100mA output from the op amp into CLcan slew VOUT at a rate of 100V/µs, far below the intrinsic AD811 slew rate of 2500V/µs. Although the drawbacks are serious, this form of cap load compensation is nevertheless useful because of its simplicity. If the amplifier is not otherwise protected, then an RX resistor of 50-100ohms should be used with virtually any amplifier facing capacitive loading. Although a non-inverting amplifier is shown, the technique is equally applicable to inverter stages. With very speed high amplifiers, or in applications where lowest settling time is critical, even small values of load capacitance can be disruptive to frequency response, but are nevertheless sometimes inescapable. One case in point is an amplifier used for driving ADC inputs. Since high speed ADC inputs quite often look capacitive in nature, this presents an oil/water type problem. In such cases the amplifier must be stable driving the capacitance, but it must also preserve its best bandwidth and settling time characteristics. To address this type of cap load case performance, Rs and CL data for a specified settling time is most appropriate. Some applications, in particular those that require driving the relatively high impedance of an ADC, do not have a convenient back termination resistor to dampen the effects of capacitive loading. At high frequencies, an amplifier’s output impedance is rising with frequency and acts like an inductance, which in combination with CL causes peaking or even worse, oscillation. When the bandwidth of an amplifier is an appreciable percentage of device ft ,the situation is complicated by the fact that the loading effects are reflected back into its internal stages. In spite of this, the basic behavior of most very wide bandwidth amplifiers such as the AD8001 is very similar. In general, a small damping resistor (Rs ) placed in series with CL will help restore the desired response (see Figure 2.4). The best choice for this resistor’s value will depend upon the criterion used in determining the desired response. Traditionally, simply stability or an acceptable amount of peaking has been used, but a more strict measure such as 0.1% (or even 0.01%) settling will yield different values. For a given amplifier, a family of Rs - CLcurves exists, such as those of Figure 2.4. These data will aid in selecting Rs for a given application
AD8001 Rs REQIRED FOR VARIOUS CL VALUES G#+2 0.1% SETTLING G=+2 20 OVERSHOOT CL (PF) Figure 2.4 The basic shape of this curve can be easily explained. When Cl is very small,no resistor is necessary. When Cl increases to some threshold value an Rs becomes necessary. Since the frequency at which the damping is required is related to the Rs CL time constant, the Rs needed will initially increase rapidly from zero, and then will decrease as Cl is increased further A relatively strict requirement, such as for 0. 1%, settling will generally require a larger Rs for a given Cl, giving a curve falling higher (in terms of rs) than that for a less stringent requirement, such as 20%overshoot. For the common gain condition of +2, these two curves are plotted in the figure for 0. 1% settling(upper-most curve)and 20% overshoot(middle curve).It is also worth mentioning that higher closed loop gains lessen the problem dramatically, and will require less Rs for the same performance. The third (lower- most)curve illustrates this, demonstrating a closed loop gain of 10 Rs requirement for 20% overshoot for the AD8001 amplifier. This can be related to the earlier discussion associated with Figure 2.2 The recommended values for Rs will optimize response, but it is important to note that generally Cl will degrade the maximum bandwidth and settling time performance which is achievable In the limit, a large Rs Cl time constant will dominate the response. In any given application, the value for Rs should be taken as a starting point in an optimization process which accounts for board parasitics and other secondary effects Active or "in-the-Loop "cap load compensation can also be used as shown in Figure 2.5, and this scheme modifies the passive configuration to prouide feedback correcti for the dc low frequency gain error associated with Rx. In contrast to the passive form, active compensation can only be used with voltage feedback amplifiers, because current feedback amplifiers don t allow the integrating connection of Cl
7 AD8001 RS REQIRED FOR VARIOUS CL VALUES Figure 2.4 The basic shape of this curve can be easily explained. When CLis very small, no resistor is necessary. When CLincreases to some threshold value an Rs becomes necessary. Since the frequency at which the damping is required is related to the Rs•CLtime constant, the Rs needed will initially increase rapidly from zero, and then will decrease as CLis increased further. A relatively strict requirement, such as for 0.1%, settling will generally require a larger Rs for a given CL, giving a curve falling higher (in terms of Rs ) than that for a less stringent requirement, such as 20% overshoot. For the common gain condition of +2, these two curves are plotted in the figure for 0.1% settling (upper-most curve) and 20% overshoot (middle curve). It is also worth mentioning that higher closed loop gains lessen the problem dramatically, and will require less Rs for the same performance. The third (lowermost) curve illustrates this, demonstrating a closed loop gain of 10 Rs requirement for 20% overshoot for the AD8001 amplifier. This can be related to the earlier discussion associated with Figure 2.2. The recommended values for Rs will optimize response, but it is important to note that generally CLwill degrade the maximum bandwidth and settling time performance which is achievable. In the limit, a large Rs•CLtime constant will dominate the response. In any given application, the value for Rs should be taken as a starting point in an optimization process which accounts for board parasitics and other secondary effects. Active or “in-the-loop” cap load compensation can also be used as shown in Figure 2.5, and this scheme modifies the passive configuration to provide feedback correction for the DC & low frequency gain error associated with RX. In contrast to the passive form, active compensation can only be used with voltage feedback amplifiers, because current feedback amplifiers don’t allow the integrating connection of CF
ACTIVE“ N-LOOP” CAPACITIVE LOAD COMPENSATION CORRECTS FOR DC AND LF GAIN ERRORS Rx AD845 RL 5000 2.5k 2.5kQ Figure 2.5 This circuit returns the DC feedback from the output side of isolation resistor Rx, thus correcting for errors. AC feedback is returned via CF, which bypasses RX/RFat high frequencies. With an appropriate value of CF(which varies with Cl, for fixed resistances)this stage can be adjusted for a well damped transient response (Reference 2, 3). There is still a bandwidth reduction, a headroom loss, and also (usually)a slew rate reduction, but the dc errors can be very low. a drawback is the need to tune CF to Cl, as even if this is done well initially, any change to Cl will alter the response away from flat. The circuit as shown is useful for voltage feedback amplifiers only, because capacitor Cf provides integration around Ul. It also can be implemented in inverting fashion, by driving the bottom end of rin Internal cap load compensation inuolves the use of an amplifier which internally has topological provisions for the effects of external cap loading. To the user, this is the most transparent of the various techniques, as it works for any feedback situation, for does an otherwise similar amplifier without the network, and the compensate> than any value of load capacitance. Drawbacks are that it produces higher distortion against cap loading is somewhat signal level dependent
8 ACTIVE “IN-LOOP” CAPACITIVE LOAD COMPENSATION CORRECTS FOR DC AND LF GAIN ERRORS Figure 2.5 This circuit returns the DC feedback from the output side of isolation resistor RX, thus correcting for errors. AC feedback is returned via CF, which bypasses RX/RFat high frequencies. With an appropriate value of CF (which varies with CL, for fixed resistances) this stage can be adjusted for a well damped transient response (Reference 2,3). There is still a bandwidth reduction, a headroom loss, and also (usually) a slew rate reduction, but the DC errors can be very low. A drawback is the need to tune CF to CL, as even if this is done well initially, any change to CL will alter the response away from flat. The circuit as shown is useful for voltage feedback amplifiers only, because capacitor CF provides integration around U1. It also can be implemented in inverting fashion, by driving the bottom end of RIN. Internal cap load compensation involves the use of an amplifier which internally has topological provisions for the effects of external cap loading. To the user, this is the most transparent of the various techniques, as it works for any feedback situation, for any value of load capacitance. Drawbacks are that it produces higher distortion than does an otherwise similar amplifier without the network, and the compensation against cap loading is somewhat signal level dependent
AD817 SIMPLIFIED SCHEMATIC ILLUSTRATES INTERNAL COMPENSATION FOR DRIVING CAPACITIVE LOADS OUTPUT 8 NULL 1 NULL 8 Figure 2.6 The internal cap load compensated amplifier sounds at first like the best of all possible worlds, since the user need do nothing at all to set it up Figure 2.6,a simplified diagram of an amplifier with internal cap load compensation, shows how it works. The cap load compensation is the CF -resistor network shown around the unity gain output stage of the amplifier. note that the dotted connection of this network underscores the fact that it only makes its presence felt for certain load conditions Under normal (non-capacitive or light resistive) loading, there is limited input/output voltage error across the output stage, so the CF network then sees relatively small voltage drop and has little or no effect on the amplifiers high impedance compensation node. However when a capacitor(or other heavy) load is present, the high currents in the output stage produce a voltage difference across the CF network, which effectively adds capacitance to the compensation node. With this elatively heavy loading, a net larger compensation capacitance results, and reduces the amplifier speed in a manner which is adaptive to the external capacitance, CL As a point of reference, note that it requires 6 3mA peak to support a 2Vp-p swing across a 100pF load at 10MHz Since this mechanism is resident in the amplifier output stage and it affects the overall compensation characteristics dynamically, it acts independent of the specific
9 AD817 SIMPLIFIED SCHEMATIC ILLUSTRATES INTERNAL COMPENSATION FOR DRIVING CAPACITIVE LOADS Figure 2.6 The internal cap load compensated amplifier sounds at first like the best of all possible worlds, since the user need do nothing at all to set it up. Figure 2.6, a simplified diagram of an amplifier with internal cap load compensation, shows how it works. The cap load compensation is the CF -resistor network shown around the unity gain output stage of the amplifier - note that the dotted connection of this network underscores the fact that it only makes its presence felt for certain load conditions. Under normal (non-capacitive or light resistive) loading, there is limited input/output voltage error across the output stage, so the CF network then sees a relatively small voltage drop, and has little or no effect on the amplifier’s high impedance compensation node. However when a capacitor (or other heavy) load is present, the high currents in the output stage produce a voltage difference across the CF network, which effectively adds capacitance to the compensation node. With this relatively heavy loading, a net larger compensation capacitance results, and reduces the amplifier speed in a manner which is adaptive to the external capacitance, CL. As a point of reference, note that it requires 6.3mA peak to support a 2Vp-p swing across a 100pF load at 10MHz. Since this mechanism is resident in the amplifier output stage and it affects the overall compensation characteristics dynamically, it acts independent of the specific
feedback hookup, as well as size of the external cap loading. In other words, it can be transparent to the user in the sense that no specific design conditions need be set to make it work(other than selecting an ic which employs it). Some amplifiers using internal cap load compensation are the AD8 47 and the AD817, and their dual equivalents, AD827 and AD826 There are, however, some caveats also associated with this internal compensation scheme. As with the passive compensation techniques, bandwidth decreases as the device slows down to prevent oscillation with higher load currents. Also, this adaptive compensation network has its greatest effect when enough output current flows to produce significant voltage drop across the CF network. Conversely, at small signal levels, the effect of the network on speed is less, so greater ringing may actually be possible for some circuits for lower-level outputs. RESPONSE OF INTERNAL CAP LOAD COMPENSATED AMPLIFIER VARIES WITH SIGNAL LEVEL (A) VOUT = 10V p-p (B)VOUT 200mv p-p Vertical Scale: 5V/div Vertical Scale, 100m Vldiv ■■■ ■■■■■ ■■■■■ ■■■■■■■ ■■■■■■ ■□- □〓i Horizontal Scale: 500ns/div AD817 INVERTER RF ERIN = 1kQ2 RL= lkQ2, CL= InF, Vs =t15V Figure 2.7 The dynamic nature of this internal cap load compensation is illustrated in Figure 2.7, which shows an AD8 17 unity gain inverter being exercised at both high and low output levels, with common conditions of Vs=+15V, Rl= 1kohm, CL= InF, and using 1kohm input/feedback resistors. In both photos the input signal is on the top trace and the output signal is on the bottom trace, and the time scale is fixed. In the 10Vp-p output(A) photo at the left, the output has slowed down appreciably to accommodate the capacitive load, but settling is still relatively clean, with a small percentage of overshoot. This indicates that for this high level case, the bandwidth reduction due to CL is most effective. However, in the(B) photo at the right, the 200mVp-p output shows greater overshoot and ringing, for the lower level signal The point is made that, to some degree at least, the relative cap load immunity of this type of internally cap load compensated amplifier is signal dependent
1 0 feedback hookup, as well as size of the external cap loading. In other words, it can be transparent to the user in the sense that no specific design conditions need be set to make it work (other than selecting an IC which employs it). Some amplifiers using internal cap load compensation are the AD847 and the AD817, and their dual equivalents, AD827 and AD826. There are, however, some caveats also associated with this internal compensation scheme. As with the passive compensation techniques, bandwidth decreases as the device slows down to prevent oscillation with higher load currents. Also, this adaptive compensation network has its greatest effect when enough output current flows to produce significant voltage drop across the CF network. Conversely, at small signal levels, the effect of the network on speed is less, so greater ringing may actually be possible for some circuits for lower-level outputs. RESPONSE OF INTERNAL CAP LOAD COMPENSATED AMPLIFIER VARIES WITH SIGNAL LEVEL Figure 2.7 The dynamic nature of this internal cap load compensation is illustrated in Figure 2.7, which shows an AD817 unity gain inverter being exercised at both high and low output levels, with common conditions of Vs = ±15V, RL= 1kohm, CL= 1nF, and using 1kohm input/feedback resistors. In both photos the input signal is on the top trace and the output signal is on the bottom trace, and the time scale is fixed. In the 10Vp-p output (A) photo at the left, the output has slowed down appreciably to accommodate the capacitive load, but settling is still relatively clean, with a small percentage of overshoot. This indicates that for this high level case, the bandwidth reduction due to CL is most effective. However, in the (B) photo at the right, the 200mVp-p output shows greater overshoot and ringing, for the lower level signal. The point is made that, to some degree at least, the relative cap load immunity of this type of internally cap load compensated amplifier is signal dependent