Ideal Pipeliningcombinational logic(F,D,E,M,W)BW=~(1/T)TpsecABW=~(2/T)T/2 ps (F,D,E)T/2 ps (M,W)AAAT/3T/3T/3BW=~(3/T)ps (F,D)ps (E,M)ps (M,W)AAComputerArchitecture11
Computer Architecture Ideal Pipelining 11 combinaBonal logic (F,D,E,M,W) T psec BW=~(1/T) T/2 ps (F,D,E) T/2 ps (M,W) BW=~(2/T) BW=~(3/T) T/3 ps (F,D) T/3 ps (E,M) T/3 ps (M,W)
More Realistic Pipeline: ThroughputNonpipelined version with delay TBW = 1/(T+S) where S = latch delayTpsk-stagepipelinedversionBW k-stage = 1 / (T/k +S )BWmax = 1 / (1 gate delay + S )T/kT/kpspsComputerArchitecture12
Computer Architecture More RealisBc Pipeline: Throughput • Nonpipelined version with delay T BW = 1/(T+S) where S = latch delay • k-stage pipelined version BWk-stage = 1 / (T/k +S ) BWmax = 1 / (1 gate delay + S ) 12 T ps T/k ps T/k ps
MoreRealisticPipeline:Cost: Nonpipelined version with combinational cost GCost = G+L where L = latch costGgatesk-stagepipelinedversionCostk-stage = G + LkG/kG/kComputerArchitecture13
Computer Architecture More RealisBc Pipeline: Cost • Nonpipelined version with combinaBonal cost G Cost = G+L where L = latch cost • k-stage pipelined version Costk-stage = G + Lk 13 G gates G/k G/k
Pipelining Instruction Processing14ComputerArchitecture
Computer Architecture Pipelining InstrucBon Processing 14
Remember:TheInstructionProcessing Cycle1. Instruction fetch (IF)2. Instruction decode andregisteroperandfetch(ID/RF)3.Execute/Evaluatememory address (EX/AG)4. Memory operand fetch (MEM)5.Store/writebackresult(WB)ComputerArchitecture15
Computer Architecture Remember: The InstrucBon Processing Cycle – Fetch – Decode – Evaluate Address – Fetch Operands – Execute – Store Result 15 1. Instruction fetch (IF) 2. Instruction decode and register operand fetch (ID/RF) 3. Execute/Evaluate memory address (EX/AG) 4. Memory operand fetch (MEM) 5. Store/writeback result (WB)