Table of Contents 1394 Open Host Controller Interface Specification/Release 1.1 Printed 1/10/00 Page xii Copyright 1996-2000 All rights reserved
Page xii Copyright © 1996-2000 All rights reserved. Table of Contents 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00
List of Figures 1394 Open Host Controller Interface Specification Release 1.1 Printed 1/10/00 List of Figures Figure 1-1-1394 Open HCI conceptual block diagram....3 Figure 1-2-Node Offset Map..9 Figure 3-1-ContextControl(set and clear)register format 17 Figure 3-2-CommandPtr register format 22 Figure 3-3-Flow Chart for Processing a DMA Context 24 Figure 5-1-Version register 35 Figure 5-2-GUID ROM register 6 Figure 5-3-ATRetries register 37 Figure 5-4-CSR data register 38 Figure 5--CSR compare register 39 Figure 5-6-CSR control register 39 Figure 5-7-Config ROM header register........................ 40 Figure 5-8-Bus ID register 40 Figure 5-9-Bus options register .41 Figure 5-10-GlobalUniqueIDHi register. 42 Figure 5-11-GlobalUniqueIDLo register ............. 42 Figure 5-12-Configuration ROM mapping register 44 Figure 5-13-VendorID register 44 Figure 5-14-HCControl register...... 45 Figure 5-15-Initial Bandwidth Available register....... .50 Figure 5-16-Initial Channels Available Hi register 50 Figure 5-17-Initial Channels Available Lo register 50 Figure 5-18-FairnessControl register 。2,。。，。。。。，, 51 Figure 5-19-LinkControl register............ 51 Figure 5-20-Node ID register.... 53 Figure 5-21-PHY control register 54 Figure 5-22-Isochronous cycle timer register 55 Figure 5-23-AsynchronousRequestFilterHi(set and clear)register 56 Figure 5-24-AsynchronousRequestFilterLo(set and clear)register 6 Figure 5-25-PhysicalRequestFilterHi(set and clear)register .57 Figure 5-26-PhysicalRequestFilterLo(set and clear)register 57 Figure 5-27-48-bit Physical Upper Bound ....................... 58 Figure 5-28-Physical Upper Bound register....... 58 Figure 6-1-IntEvent register.. 62 Figure 6-2-IntMask register 65 Figure 6-3-isoXmitIntEvent (set and clear)register 66 Figure 6-4-isoXmitIntMask(set and clear)register 67 Figure 6-5-isoRecvIntEvent(set and clear)register 68 Figure 6-6-isoRecvIntMask (set and clear)register 68 Figure 7-1-OUTPUT_MORE descriptor format......... 70 Figure 7-2-OUTPUT MORE-Immediate descriptor format .71 Figure 7-3-OUTPUT LAST descriptor format..................... 72 Figure 7-4-OUTPUT LAST-Immediate descriptor format 74 Figure 7-5-timeStamp format 76 Figure 7-6-CommandPtr register format ............ 80 Figure 7-7-ContextControl(set and clear)register format 80 Figure 7-8-Completion Status and Retry Behavior .82 Figure 7-9-Quadlet read request transmit format..... 84 Figure 7-10-Quadlet write request transmit format 85 Figure 7-11-Block read request transmit format........ 86 Figure 7-12-Write request transmit format............. 87 Figure 7-13-Lock request transmit format ........... .88 Copyright1996-2000 All rights reserved. Page xiii
Copyright © 1996-2000 All rights reserved. Page xiii List of Figures 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 List of Figures Figure 1-1 — 1394 Open HCI conceptual block diagram .....................................................................................................3 Figure 1-2 — Node Offset Map ............................................................................................................................................9 Figure 3-1 — ContextControl (set and clear) register format ..............................................................................................17 Figure 3-2 — CommandPtr register format .........................................................................................................................22 Figure 3-3 — Flow Chart for Processing a DMA Context ..................................................................................................24 Figure 5-1 — Version register .............................................................................................................................................35 Figure 5-2 — GUID ROM register ......................................................................................................................................36 Figure 5-3 — ATRetries register .........................................................................................................................................37 Figure 5-4 — CSR data register ..........................................................................................................................................38 Figure 5-5 — CSR compare register ...................................................................................................................................39 Figure 5-6 — CSR control register .....................................................................................................................................39 Figure 5-7 — Config ROM header register .........................................................................................................................40 Figure 5-8 — Bus ID register ..............................................................................................................................................40 Figure 5-9 — Bus options register ......................................................................................................................................41 Figure 5-10 — GlobalUniqueIDHi register .........................................................................................................................42 Figure 5-11 — GlobalUniqueIDLo register ........................................................................................................................42 Figure 5-12 — Configuration ROM mapping register .........................................................................................................44 Figure 5-13 — VendorID register ........................................................................................................................................44 Figure 5-14 — HCControl register ......................................................................................................................................45 Figure 5-15 — Initial Bandwidth Available register ............................................................................................................50 Figure 5-16 — Initial Channels Available Hi register .........................................................................................................50 Figure 5-17 — Initial Channels Available Lo register .........................................................................................................50 Figure 5-18 — FairnessControl register ..............................................................................................................................51 Figure 5-19 — LinkControl register ....................................................................................................................................51 Figure 5-20 — Node ID register .........................................................................................................................................53 Figure 5-21 — PHY control register ...................................................................................................................................54 Figure 5-22 — Isochronous cycle timer register .................................................................................................................55 Figure 5-23 — AsynchronousRequestFilterHi (set and clear) register ................................................................................56 Figure 5-24 — AsynchronousRequestFilterLo (set and clear) register ...............................................................................56 Figure 5-25 — PhysicalRequestFilterHi (set and clear) register .........................................................................................57 Figure 5-26 — PhysicalRequestFilterLo (set and clear) register .........................................................................................57 Figure 5-27 — 48-bit Physical Upper Bound ......................................................................................................................58 Figure 5-28 — Physical Upper Bound register ....................................................................................................................58 Figure 6-1 — IntEvent register ............................................................................................................................................62 Figure 6-2 — IntMask register ............................................................................................................................................65 Figure 6-3 — isoXmitIntEvent (set and clear) register ........................................................................................................66 Figure 6-4 — isoXmitIntMask (set and clear) register ........................................................................................................67 Figure 6-5 — isoRecvIntEvent (set and clear) register ........................................................................................................68 Figure 6-6 — isoRecvIntMask (set and clear) register ........................................................................................................68 Figure 7-1 — OUTPUT_MORE descriptor format .............................................................................................................70 Figure 7-2 — OUTPUT_MORE-Immediate descriptor format ...........................................................................................71 Figure 7-3 — OUTPUT_LAST descriptor format ..............................................................................................................72 Figure 7-4 — OUTPUT_LAST-Immediate descriptor format .............................................................................................74 Figure 7-5 — timeStamp format .........................................................................................................................................76 Figure 7-6 — CommandPtr register format .........................................................................................................................80 Figure 7-7 — ContextControl (set and clear) register format ..............................................................................................80 Figure 7-8 — Completion Status and Retry Behavior .........................................................................................................82 Figure 7-9 — Quadlet read request transmit format ............................................................................................................84 Figure 7-10 — Quadlet write request transmit format .........................................................................................................85 Figure 7-11 — Block read request transmit format .............................................................................................................86 Figure 7-12 — Write request transmit format .....................................................................................................................87 Figure 7-13 — Lock request transmit format ......................................................................................................................88
List of Figures 1394 Open Host Controller Interface Specification Release 1.1 Printed 1/10/00 Figure 7-14-PHY packet transmit format 89 Figure 7-15-Write response transmit format .89 Figure 7-16-Quadlet read response transmit format 90 Figure 7-17-Block read response transmit format 91 Figure 7-18-Lock response transmit format....9. Figure 7-19-Asynchronous stream packet format 。 .93 Figure 8-1-INPUT MORE descriptor format 95 Figure 8-2-bufferFill receive mode............. .97 Figure 8-3-CommandPtr register format................. 97 Figure 8-4-AR ContextControl(set and clear)register format 98 Figure 8-5-AR DMA packet trailer format............ 100 Figure 8-6-AR Request Context Bus Reset packet format ........... 101 Figure 8-7-Quadlet read request receive format ............... 104 Figure 8-8-Quadlet write request receive format 104 Figure 8-9-Block read request receive format............ 105 Figure 8-10-Block write request receive format 106 Figure 8-11-Lock request receive format..... 107 Figure 8-12-PHY packet receive format 107 Figure 8-13-Write response receive format 108 Figure 8-14-Quadlet read response receive format 108 Figure 8-15-Block read response receive format 109 Figure 8-16-Lock response receive format.............. ,110 Figure 9-1-OUTPUT_MORE command descriptor format.......... 112 Figure 9-2-OUTPUT_MORE-Immediate descriptor format ,113 Figure 9-3-OUTPUT LAST command descriptor format...................... ,114 Figure 9-4-OUTPUT_LAST-Immediate command descriptor format ,115 Figure 9-5-STORE_VALUE descriptor 116 Figure 9-6-CommandPtr register format.... 118 Figure 9-7-IT DMA ContextControl(set and clear)register format 119 Figure 9-8-ITDMA summary. 121 Figure 9-9-Isochronous transmit cycle loss example 124 Figure 9-10-Isochronous transmit format 126 Figure 10-1-INPUT_MORE/INPUT_LAST descriptor format ...... 129 Figure 10-2-DUALBUFFER descriptor format............... 131 Figure 10-3-IR Buffer Fill Mode............................. 133 Figure 10-4-packet-per-buffer receive mode............... 134 Figure 10-5-IR Dual-Buffer Mode........ 136 Figure 10-6-CommandPtr register format.... 137 Figure 10-7-IR DMA ContextControl(set and clear)register format 138 Figure 10-8-IR DMA ContextMatch register format ......... 140 Figure 10-9-IRMultiChanMaskHi (set and clear)register ..................... 141 Figure 10-10-IRMultiChanMaskLo(set and clear)register.... 142 Figure 10-11-Receive isochronous format in bufferFill mode with header/trailer .............................. 144 Figure 10-12-Receive isochronous format in bufferFill mode without header/trailer................. .145 Figure 10-13-Receive isochronous format in packet-per-buffer or dual-buffer mode with header/trailer...................145 Figure 10-14-Receive isochronous format in packet-per-buffer and dual-buffer mode without header/trailer 146 Figure 11-1-Self IDBuffer pointer register. .147 Figure 11-2-SelfID Count register... 147 Figure 11-3-Self-ID receive format 148 Figure 13-1-PostedWriteAddressHi register..... 156 Figure 13-2-PostedWriteAddressLo register ,156 Figure 13-3-Posted Write Error Queue 157 Figure A-1-PCI Configuration Space... 159 Figure A-2-Pointers to OHCI Resources in PCI Configuration Space 160 Page xiv Copyright1996-2000 All rights reserved
Page xiv Copyright © 1996-2000 All rights reserved. List of Figures 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 Figure 7-14 — PHY packet transmit format .......................................................................................................................89 Figure 7-15 — Write response transmit format ...................................................................................................................89 Figure 7-16 — Quadlet read response transmit format .......................................................................................................90 Figure 7-17 — Block read response transmit format ..........................................................................................................91 Figure 7-18 — Lock response transmit format ....................................................................................................................92 Figure 7-19 — Asynchronous stream packet format ..........................................................................................................93 Figure 8-1 — INPUT_MORE descriptor format .................................................................................................................95 Figure 8-2 — bufferFill receive mode .................................................................................................................................97 Figure 8-3 — CommandPtr register format .........................................................................................................................97 Figure 8-4 — AR ContextControl (set and clear) register format .......................................................................................98 Figure 8-5 — AR DMA packet trailer format ...................................................................................................................100 Figure 8-6 — AR Request Context Bus Reset packet format ............................................................................................101 Figure 8-7 — Quadlet read request receive format ...........................................................................................................104 Figure 8-8 — Quadlet write request receive format ..........................................................................................................104 Figure 8-9 — Block read request receive format ...............................................................................................................105 Figure 8-10 — Block write request receive format ...........................................................................................................106 Figure 8-11 — Lock request receive format ......................................................................................................................107 Figure 8-12 — PHY packet receive format .......................................................................................................................107 Figure 8-13 — Write response receive format ..................................................................................................................108 Figure 8-14 — Quadlet read response receive format .......................................................................................................108 Figure 8-15 — Block read response receive format ..........................................................................................................109 Figure 8-16 — Lock response receive format ...................................................................................................................110 Figure 9-1 — OUTPUT_MORE command descriptor format ..........................................................................................112 Figure 9-2 — OUTPUT_MORE-Immediate descriptor format .........................................................................................113 Figure 9-3 — OUTPUT_LAST command descriptor format ............................................................................................114 Figure 9-4 — OUTPUT_LAST-Immediate command descriptor format ..........................................................................115 Figure 9-5 — STORE_VALUE descriptor ........................................................................................................................116 Figure 9-6 — CommandPtr register format .......................................................................................................................118 Figure 9-7 — IT DMA ContextControl (set and clear) register format .............................................................................119 Figure 9-8 — IT DMA summary ......................................................................................................................................121 Figure 9-9 — Isochronous transmit cycle loss example ....................................................................................................124 Figure 9-10 — Isochronous transmit format ....................................................................................................................126 Figure 10-1 — INPUT_MORE/INPUT_LAST descriptor format ....................................................................................129 Figure 10-2 — DUALBUFFER descriptor format ............................................................................................................131 Figure 10-3 — IR Buffer Fill Mode ..................................................................................................................................133 Figure 10-4 — packet-per-buffer receive mode .................................................................................................................134 Figure 10-5 — IR Dual-Buffer Mode ................................................................................................................................136 Figure 10-6 — CommandPtr register format .....................................................................................................................137 Figure 10-7 — IR DMA ContextControl (set and clear) register format ...........................................................................138 Figure 10-8 — IR DMA ContextMatch register format ....................................................................................................140 Figure 10-9 — IRMultiChanMaskHi (set and clear) register ............................................................................................141 Figure 10-10 — IRMultiChanMaskLo (set and clear) register ..........................................................................................142 Figure 10-11 — Receive isochronous format in bufferFill mode with header/trailer ........................................................144 Figure 10-12 — Receive isochronous format in bufferFill mode without header/trailer ...................................................145 Figure 10-13 — Receive isochronous format in packet-per-buffer or dual-buffer mode with header/trailer .....................145 Figure 10-14 — Receive isochronous format in packet-per-buffer and dual-buffer mode without header/trailer ..............146 Figure 11-1 — Self ID Buffer Pointer register ..................................................................................................................147 Figure 11-2 — Self ID Count register ...............................................................................................................................147 Figure 11-3 — Self-ID receive format ..............................................................................................................................148 Figure 13-1 — PostedWriteAddressHi register .................................................................................................................156 Figure 13-2 — PostedWriteAddressLo register ................................................................................................................156 Figure 13-3 — Posted Write Error Queue .........................................................................................................................157 Figure A-1 — PCI Configuration Space ...........................................................................................................................159 Figure A-2 — Pointers to OHCI Resources in PCI Configuration Space ..........................................................................160
List of Figures 1394 Open Host Controller Interface Specification/Release 1.1 Printed 1/10/00 Figure A-3-PCI Function Power Management State Diagram..............166 Figure D-1-ITDMA DMA-Side Flowchart...180 Figure D-2-IT DMA Link-Side Flowchart....... 183 Figure E-1-DMA Cycle Matching Continuum185 Figure E-2-IT DMA Controller counters and cycle matching logic 186 Figure E-3-IT DMA Flowchart..... 187 Figure E-4-Process IT Contexts Flowchart.................. 188 Figure E-5-Skip IT Contexts Flowchart........... 189 Figure F-1-GUID ROM data map...... 191 Figure F-2-Mini-ROM format ................ 191 Copyright1996-2000 All rights reserved. Page xv
Copyright © 1996-2000 All rights reserved. Page xv List of Figures 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 Figure A-3 — PCI Function Power Management State Diagram ......................................................................................166 Figure D-1 — IT DMA DMA-Side Flowchart ..................................................................................................................180 Figure D-2 — IT DMA Link-Side Flowchart ...................................................................................................................183 Figure E-1 — DMA Cycle Matching Continuum .............................................................................................................185 Figure E-2 — IT DMA Controller counters and cycle matching logic ..............................................................................186 Figure E-3 — IT DMA Flowchart .....................................................................................................................................187 Figure E-4 — Process IT Contexts Flowchart ...................................................................................................................188 Figure E-5 — Skip IT Contexts Flowchart ........................................................................................................................189 Figure F-1 — GUID ROM data map .................................................................................................................................191 Figure F-2 — Mini-ROM format ......................................................................................................................................191
List of Tables 1394 Open Host Controller Interface Specification Release 1.1 Printed 1/10/00 List of Tables Table 1-1-DMA controller types and contexts4 Table 1-2-Link generated acknowledges Table 2-1-read/write register field access tags 12 Table 2-2-Set and Clear register field access tags 12 Table 2-3-Register field reset values....... 13 Table 3-1-ContextControl (set and clear)register description 17 Table 3-2-Packet event codes 18 Table 3-3-CommandPtr register description ............ 22 Table 3-4-CommandPtr read values ....................... 22 Table 3-5-DMA Summary. 28 Table 4-1-1394 Open HCI register space map 30 Table 4-2-Asynchronous DMA Context number assignments 30 Table 4-3-Register addresses (Sheet I of4) .30 Table 5-1-Version register fields 35 Table 5-2-GUID ROM register fields 36 Table 5-3-ATRetries register fields 3 Table 5-4-Serial Bus Registers.... 38 Table 5-5-CSR registers'fields 39 Table 5-6-Config ROM header register fields... 40 Table 5-7-Bus ID register fields..................... 40 Table 5-8-Bus options register fields... 41 Table 5-9-GlobalUniquelD register fields.... 42 Table 5-10-Configuration ROM mapping register fields........ 44 Table 5-11-VendorID register fields..... 44 Table 5-12-HCControl register fields... 45 Table 5-13-programPhyEnable and aPhy EnhanceEnable Examples 48 Table 5-14-LPS and linkEnable assertion 49 Table 5-15-Bus Management CSR Initialization registers'fields 50 Table 5-16-FairnessControl register fields 51 Table 5-17-LinkControl register fields .52 Table 5-18-Node ID register fields .53 Table 5-19-PHY control register fields 54 Table 5-20-Isochronous cycle timer register fields 55 Table 5-21-AsynchronousRequestFilter register fields.............. 56 Table 5-22-PhysicalRequestFilter register fields 57 Table 5-23-Physical Upper Bound register fields 59 Table 6-1-IntEvent register description(Sheet 1 of 3) 62 Table 6-2-IntMask register description......... 65 Table 7-1-OUTPUT MORE descriptor element summary 70 Table 7-2-OUTPUT_MORE-Immediate descriptor element summary 71 Table 7-3-OUTPUT LAST descriptor element summary ....................... 72 Table 7-4-OUTPUT LAST-Immediate descriptor element summary 74 Table 7-5-2value encoding 76 Table 7-6-timeStamp description ................ .77 Table 7-7-Results of timeStamp.cycleSeconds-cycleTimer.cycleSeconds 18 Table 7-8-timeStamp.cycleCount-cycleTime.cycleCount Example 1.................... 78 Table 7-9-timeStamp.cycleCount-cycleTime.cycleCount Example 2..... 78 Table 7-10-timeStamp.cycleCount-cycleTime.cycleCount Example 3 79 Table 7-11-ContextControl (set and clear)register description 81 Table 7-12-Quadlet read request transmit fields .84 Table 7-13-Quadlet transmit fields 86 Table 7-14-Block transmit fields............. 88 Copyright1996-2000 All rights reserved. Page xvii
Copyright © 1996-2000 All rights reserved. Page xvii List of Tables 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 List of Tables Table 1-1 — DMA controller types and contexts ..................................................................................................................4 Table 1-2 — Link generated acknowledges ...........................................................................................................................7 Table 2-1 — read/write register field access tags ................................................................................................................12 Table 2-2 — Set and Clear register field access tags ...........................................................................................................12 Table 2-3 — Register field reset values ...............................................................................................................................13 Table 3-1 — ContextControl (set and clear) register description ........................................................................................17 Table 3-2 — Packet event codes ..........................................................................................................................................18 Table 3-3 — CommandPtr register description ...................................................................................................................22 Table 3-4 — CommandPtr read values ................................................................................................................................22 Table 3-5 — DMA Summary ..............................................................................................................................................28 Table 4-1 — 1394 Open HCI register space map ................................................................................................................30 Table 4-2 — Asynchronous DMA Context number assignments ........................................................................................30 Table 4-3 — Register addresses (Sheet 1 of 4) ....................................................................................................................30 Table 5-1 — Version register fields .....................................................................................................................................35 Table 5-2 — GUID ROM register fields ..............................................................................................................................36 Table 5-3 — ATRetries register fields ................................................................................................................................37 Table 5-4 — Serial Bus Registers ........................................................................................................................................38 Table 5-5 — CSR registers’ fields ......................................................................................................................................39 Table 5-6 — Config ROM header register fields .................................................................................................................40 Table 5-7 — Bus ID register fields ......................................................................................................................................40 Table 5-8 — Bus options register fields ..............................................................................................................................41 Table 5-9 — GlobalUniqueID register fields .......................................................................................................................42 Table 5-10 — Configuration ROM mapping register fields ................................................................................................44 Table 5-11 — VendorID register fields ...............................................................................................................................44 Table 5-12 — HCControl register fields ..............................................................................................................................45 Table 5-13 — programPhyEnable and aPhyEnhanceEnable Examples ...............................................................................48 Table 5-14 — LPS and linkEnable assertion .......................................................................................................................49 Table 5-15 — Bus Management CSR Initialization registers’ fields ..................................................................................50 Table 5-16 — FairnessControl register fields .....................................................................................................................51 Table 5-17 — LinkControl register fields ...........................................................................................................................52 Table 5-18 — Node ID register fields ................................................................................................................................53 Table 5-19 — PHY control register fields ..........................................................................................................................54 Table 5-20 — Isochronous cycle timer register fields .........................................................................................................55 Table 5-21 — AsynchronousRequestFilter register fields ...................................................................................................56 Table 5-22 — PhysicalRequestFilter register fields .............................................................................................................57 Table 5-23 — Physical Upper Bound register fields ...........................................................................................................59 Table 6-1 — IntEvent register description (Sheet 1 of 3) ....................................................................................................62 Table 6-2 — IntMask register description ..........................................................................................................................65 Table 7-1 — OUTPUT_MORE descriptor element summary .............................................................................................70 Table 7-2 — OUTPUT_MORE-Immediate descriptor element summary ...........................................................................71 Table 7-3 — OUTPUT_LAST descriptor element summary ...............................................................................................72 Table 7-4 — OUTPUT_LAST-Immediate descriptor element summary .............................................................................74 Table 7-5 — Z value encoding ............................................................................................................................................76 Table 7-6 — timeStamp description ....................................................................................................................................77 Table 7-7 — Results of timeStamp.cycleSeconds - cycleTimer.cycleSeconds ....................................................................78 Table 7-8 — timeStamp.cycleCount-cycleTime.cycleCount Example 1 .............................................................................78 Table 7-9 — timeStamp.cycleCount-cycleTime.cycleCount Example 2 .............................................................................78 Table 7-10 — timeStamp.cycleCount-cycleTime.cycleCount Example 3 ...........................................................................79 Table 7-11 — ContextControl (set and clear) register description ......................................................................................81 Table 7-12 — Quadlet read request transmit fields ............................................................................................................84 Table 7-13 — Quadlet transmit fields ................................................................................................................................86 Table 7-14 — Block transmit fields ....................................................................................................................................88