List of Tables 1394 Open Host Controller Interface Specification/Release 1.1 Printed 1/10/00 Table 7-15-Write response transmit fields .90 Table 7-16-Quadlet transmit fields S.91 Table 7-17-Block transmit fields 92 Table 7-18-Asynchronous stream packet fields .93 Table 8-1-INPUT MORE descriptor element summary...95. Table 8-2-AR ContextControl(set and clear)register description 98 Table 8-3-AR DMA trailer fields ,100 Table 8-4-AR Request Context Bus Reset packet description 101 Table 8-5-Asynch receive fields 103 Table 9-1-OUTPUT MORE descriptor element summary............................ -112 Table 9-2-OUTPUT MORE-Immediate descriptor element summary ................... ,113 Table 9-3-OUTPUT LAST descriptor element summary... 114 Table 9-4-OUTPUT LAST-Immediate descriptor element summary .115 Table 9-5-STORE VALUE descriptor element summary 116 Table 9-6-2value encoding 117 Table 9-7-IT DMA ContextControl(set and clear)register description .119 Table 9-8-Isochronous transmit fields... 126 Table 10-1-INPUT MORE/INPUT LAST descriptor element summary .129 Table 10-2-DUALBUFFER descriptor element summary 131 Table 10-3-Z value encoding........ 132 Table 10-4-IR DMA ContextControl(set and clear)register description 138 Table 10-5-IR DMA ContextMatch register description............. .140 Table 10-6-Isochronous receive fields ...................... ..143 Table 11-1-Self ID Buffer Pointer register........ .147 Table 11-2-Self ID Count register............... 147 Table 11-3-Self-ID receive fields 148 Table 13-1-PostedWriteAddress register description 156 Table A-1-COMMAND Register 160 Table A-2-STATUS Register................ 161 Table A-3-CLASS CODE Register 161 Table A-4-Base Adr 0 Register 162 Table A-5-CAP_PTR Register 162 Table A-6-PCI HCI Control Register.... .163 Table A-7-Capability ID Register.............. ,163 Table A-8-Next Item Pointer Register......... 163 Table A-9-PMC Register. 164 Table A-10-PM Control/Status Register 165 Table A-11-Open HCI Power State Summary 167 Table B-1-Register Reset Summary 171 Page xviii Copyright 1996-2000 All rights reserved
Page xviii Copyright © 1996-2000 All rights reserved. List of Tables 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 Table 7-15 — Write response transmit fields .....................................................................................................................90 Table 7-16 — Quadlet transmit fields ................................................................................................................................91 Table 7-17 — Block transmit fields ...................................................................................................................................92 Table 7-18 — Asynchronous stream packet fields .............................................................................................................93 Table 8-1 — INPUT_MORE descriptor element summary .................................................................................................95 Table 8-2 — AR ContextControl (set and clear) register description ..................................................................................98 Table 8-3 — AR DMA trailer fields ..................................................................................................................................100 Table 8-4 — AR Request Context Bus Reset packet description ......................................................................................101 Table 8-5 — Asynch receive fields ...................................................................................................................................103 Table 9-1 — OUTPUT_MORE descriptor element summary ...........................................................................................112 Table 9-2 — OUTPUT_MORE-Immediate descriptor element summary .........................................................................113 Table 9-3 — OUTPUT_LAST descriptor element summary ............................................................................................114 Table 9-4 — OUTPUT_LAST-Immediate descriptor element summary ...........................................................................115 Table 9-5 — STORE_VALUE descriptor element summary .............................................................................................116 Table 9-6 — Z value encoding ..........................................................................................................................................117 Table 9-7 — IT DMA ContextControl (set and clear) register description ........................................................................119 Table 9-8 — Isochronous transmit fields ..........................................................................................................................126 Table 10-1 — INPUT_MORE/INPUT_LAST descriptor element summary .....................................................................129 Table 10-2 — DUALBUFFER descriptor element summary ............................................................................................131 Table 10-3 — Z value encoding ........................................................................................................................................132 Table 10-4 — IR DMA ContextControl (set and clear) register description .....................................................................138 Table 10-5 — IR DMA ContextMatch register description ...............................................................................................140 Table 10-6 — Isochronous receive fields ..........................................................................................................................143 Table 11-1 — Self ID Buffer Pointer register ....................................................................................................................147 Table 11-2 — Self ID Count register .................................................................................................................................147 Table 11-3 — Self-ID receive fields ..................................................................................................................................148 Table 13-1 — PostedWriteAddress register description ....................................................................................................156 Table A-1 — COMMAND Register ..................................................................................................................................160 Table A-2 — STATUS Register .........................................................................................................................................161 Table A-3 — CLASS_CODE Register ..............................................................................................................................161 Table A-4 — Base_Adr_0 Register ...................................................................................................................................162 Table A-5 — CAP_PTR Register ......................................................................................................................................162 Table A-6 — PCI_HCI_Control Register ..........................................................................................................................163 Table A-7 — Capability ID Register .................................................................................................................................163 Table A-8 — Next Item Pointer Register ..........................................................................................................................163 Table A-9 — PMC Register ..............................................................................................................................................164 Table A-10 — PM Control/Status Register .......................................................................................................................165 Table A-11 — Open HCI Power State Summary ..............................................................................................................167 Table B-1 — Register Reset Summary ..............................................................................................................................171
Introduction 1394 Open Host Controller Interface Specification Release 1.1 Printed 1/10/00 1.Introduction 1.1 Related documents The following documents may be useful in understanding the terms and concepts used in this specification.The docu- ments are for general background purposes only and are not incorporated into and do not form a part of this specification. [A]IEEE 1394-1995 High Performance Serial Bus IEEE.1995 [B] ISO/IEC 13213:1994 Control and Status Register Architecture for Microcomputer Busses International Standards Organization,1994 [C]IEEE1394a-2000 IEEE Standard for a High Performance Serial bus(Supplement) All references to 1394 in this document refer to IEEE 1394-1995([A]above)unless otherwise specified. Following IEEE conventions,the term"quadlet"is used throughout this document to specify a 32-bit word. 1.2 Overview The 1394 Open Host Controller Interface(Open HCI)is an implementation of the link layer protocol of the 1394 Serial Bus,with additional features to support the transaction and bus management layers.The 1394 Open HCI also includes DMA engines for high-performance data transfer and a host bus interface. IEEE 1394 (and the 1394 Open HCI)supports two types of data transfer:asynchronous and isochronous.Asynchronous data transfer puts the emphasis on guaranteed delivery of data,with less emphasis on guaranteed timing.Isochronous data transfer is the opposite,with the emphasis on the guaranteed timing of the data,and less emphasis on delivery. 1.2.1 Asynchronous functions The 1394 Open HCI can transmit and receive all of the defined 1394 packet formats.Packets to be transmitted are read out of host memory and received packets are written into host memory,both using DMA.The 1394 Open HCI can also be programmed to act as a bus bridge between host bus and 1394 by directly executing 1394 read and write requests as reads and writes to host bus memory space. 1.2.2 Isochronous functions The 1394 Open HCI is capable of performing the cycle master function as defined by 1394.This means it contains a cycle timer and counter,and can queue the transmission of a special packet called a"cycle start"after every rising edge of the 8 kHz cycle clock.The 1394 Open HCI can generate the cycle clock internally (required)or use an external reference (optional).When not the cycle master,the 1394 Open HCI keeps its internal cycle timer synchronized with the cycle master node by correcting its own cycle timer with the reload value from the cycle start packet. Conceptually,the 1394 Open HCI supports one DMA controller each for isochronous transmit and isochronous receive. Each DMA controller may be implemented to support up to 32 different DMA channels,referred to as DMA contexts within this document. The isochronous transmit DMA controller can transmit from each context during each cycle.Each context can transmit data for a single isochronous channel. Copyright 1996-2000 All rights reserved. Page 1
Copyright © 1996-2000 All rights reserved. Page 1 Introduction 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 1. Introduction 1.1 Related documents The following documents may be useful in understanding the terms and concepts used in this specification. The documents are for general background purposes only and are not incorporated into and do not form a part of this specification. [A] IEEE 1394-1995 High Performance Serial Bus IEEE, 1995 [B] ISO/IEC 13213:1994 Control and Status Register Architecture for Microcomputer Busses International Standards Organization, 1994 [C] IEEE 1394a-2000 IEEE Standard for a High Performance Serial bus (Supplement) All references to 1394 in this document refer to IEEE 1394-1995 ([A] above) unless otherwise specified. Following IEEE conventions, the term “quadlet” is used throughout this document to specify a 32-bit word. 1.2 Overview The 1394 Open Host Controller Interface (Open HCI) is an implementation of the link layer protocol of the 1394 Serial Bus, with additional features to support the transaction and bus management layers. The 1394 Open HCI also includes DMA engines for high-performance data transfer and a host bus interface. IEEE 1394 (and the 1394 Open HCI) supports two types of data transfer: asynchronous and isochronous. Asynchronous data transfer puts the emphasis on guaranteed delivery of data, with less emphasis on guaranteed timing. Isochronous data transfer is the opposite, with the emphasis on the guaranteed timing of the data, and less emphasis on delivery. 1.2.1 Asynchronous functions The 1394 Open HCI can transmit and receive all of the defined 1394 packet formats. Packets to be transmitted are read out of host memory and received packets are written into host memory, both using DMA. The 1394 Open HCI can also be programmed to act as a bus bridge between host bus and 1394 by directly executing 1394 read and write requests as reads and writes to host bus memory space. 1.2.2 Isochronous functions The 1394 Open HCI is capable of performing the cycle master function as defined by 1394. This means it contains a cycle timer and counter, and can queue the transmission of a special packet called a “cycle start” after every rising edge of the 8 kHz cycle clock. The 1394 Open HCI can generate the cycle clock internally (required) or use an external reference (optional). When not the cycle master, the 1394 Open HCI keeps its internal cycle timer synchronized with the cycle master node by correcting its own cycle timer with the reload value from the cycle start packet. Conceptually, the 1394 Open HCI supports one DMA controller each for isochronous transmit and isochronous receive. Each DMA controller may be implemented to support up to 32 different DMA channels, referred to as DMA contexts within this document. The isochronous transmit DMA controller can transmit from each context during each cycle. Each context can transmit data for a single isochronous channel
Introduction 1394 Open Host Controller Interface Specification/Release 1.1 Printed 1/10/00 The isochronous receive DMA controller can receive data for each context during each cycle.Each context can be config- ured to receive data from a single isochronous channel.Additionally,one context can be configured to receive data from multiple isochronous channels. 1.2.3 Miscellaneous functions Upon detecting a bus reset,the 1394 Open HCI automatically flushes all packets queued for asynchronous transmission. Asynchronous packet reception continues without interruption,and a token appears in the received request packet stream to indicate the occurrence of the bus reset.When the PHY provides the new local node ID,the 1394 Open HCI loads this value into its Node ID register.Asynchronous packet transmit will not resume until directed to by software.Because target node ID values may have changed during the bus reset,software will not generally be able to re-issue old asynchro- nous requests until software has determined the new target node IDs. Isochronous transmit and receive functions are not halted by a bus reset;instead they restart as soon as the bus initializa- tion process is complete. A number of management functions are also implemented by the 1394 Open HCI: a)A global unique ID register of 64 bits which can only be written once.For full compliance with higher level standards,this register shall be written before the boot block is read.To make this implementation simpler,the 1394 Open HCI optionally has an interface to an external hardware global unique ID(GUID,also known as the IEEE EUI-64). b)Four registers that implement the compare-swap operation needed for isochronous resource management. Page 2 Copyright 1996-2000 All rights reserved
Page 2 Copyright © 1996-2000 All rights reserved. Introduction 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 The isochronous receive DMA controller can receive data for each context during each cycle. Each context can be configured to receive data from a single isochronous channel. Additionally, one context can be configured to receive data from multiple isochronous channels. 1.2.3 Miscellaneous functions Upon detecting a bus reset, the 1394 Open HCI automatically flushes all packets queued for asynchronous transmission. Asynchronous packet reception continues without interruption, and a token appears in the received request packet stream to indicate the occurrence of the bus reset. When the PHY provides the new local node ID, the 1394 Open HCI loads this value into its Node ID register. Asynchronous packet transmit will not resume until directed to by software. Because target node ID values may have changed during the bus reset, software will not generally be able to re-issue old asynchronous requests until software has determined the new target node IDs. Isochronous transmit and receive functions are not halted by a bus reset; instead they restart as soon as the bus initialization process is complete. A number of management functions are also implemented by the 1394 Open HCI: a) A global unique ID register of 64 bits which can only be written once. For full compliance with higher level standards, this register shall be written before the boot block is read. To make this implementation simpler, the 1394 Open HCI optionally has an interface to an external hardware global unique ID (GUID, also known as the IEEE EUI-64). b) Four registers that implement the compare-swap operation needed for isochronous resource management
Introduction 1394 Open Host Controller Interface Specification/Release 1.1 Printed 1/10/00 1.3 Hardware description Figure 1-1 provides a conceptual block diagram of the 1394 Open HCI,and its connections in the host system.The 1394 Open HCI attaches to the host via the host bus.The host bus is assumed to be at least 32 bits wide with adequate perfor- mance to support the data rate of the particular implementation(100Mbit/sec or higher plus overhead for DMA structures) as well as bounded latency so that the FIFO's can have a reasonable size. IT T DMA FIFO AT Request AT Request DMA FIFO AT Response AT Response DMA FIFO Physical Re- 思 AT Physical sponse Unit esponse FIFO host bus (Jejsew internal registers 1394 bus Phys Read Physical Read m 13H snq) Request Rcv Request FIFO I pue Phys Write Physical Write Request Rcv Request FIFO Gen Request AR Request Serial Receive DMA FIFO ROM(Opt) Gen Response AR Response Receive DMA FIFO Parallel ROM(Opt) IR IR DMA FIFO Self-ID Self-ID Receive Receive DMA FIFO Figure 1-1-1394 Open HCI conceptual block diagram 1.3.1 Host bus interface This block acts both as a master and a slave on the host bus.As a slave,it decodes and responds to register access within the 1394 Open HCI.As a master,it acts on behalf of the 1394 Open HCI DMA units to generate transactions on the host bus.These transactions are used to move streams of data between system memory and the devices,as well as to read and write the DMA command lists. Copyright 1996-2000 All rights reserved Page3
Copyright © 1996-2000 All rights reserved. Page 3 Introduction 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 1.3 Hardware description Figure 1-1 provides a conceptual block diagram of the 1394 Open HCI, and its connections in the host system. The 1394 Open HCI attaches to the host via the host bus. The host bus is assumed to be at least 32 bits wide with adequate performance to support the data rate of the particular implementation (100Mbit/sec or higher plus overhead for DMA structures) as well as bounded latency so that the FIFO’s can have a reasonable size. 1.3.1 Host bus interface This block acts both as a master and a slave on the host bus. As a slave, it decodes and responds to register access within the 1394 Open HCI. As a master, it acts on behalf of the 1394 Open HCI DMA units to generate transactions on the host bus. These transactions are used to move streams of data between system memory and the devices, as well as to read and write the DMA command lists. Figure 1-1 — 1394 Open HCI conceptual block diagram host bus 1394 bus 1394 Link and PHY Host Bus Interface (bus master) IT DMA Physical Read Request FIFO S W A P IT FIFO S W A P AT Request FIFO S W A P AT Response FIFO S W A P AT Physical Response FIFO S W A P Physical Write Request FIFO S W A P AR Request FIFO S W A P AR Response FIFO S W A P IR FIFO S W A P Self-ID Receive FIFO AT Request DMA AT Response DMA Physical Response Unit Phys Read Request Rcv Phys Write Request Rcv Gen Request Receive DMA Gen Response Receive DMA IR DMA Self-ID Receive DMA internal registers Serial ROM (Opt) Parallel ROM (Opt)
Introduction 1394 Open Host Controller Interface Specification Release 1.1 Printed 1/10/00 1.3.2DMA The 1394 Open HCI supports seven types of DMA.Each type of DMA has reserved register space and can support at least one distinct logical data stream referred to as a DMA context. Table 1-1-DMA controller types and contexts DMA controller type number of contexts Asynchronous Transmit 1 Request,1 Response Asynchronous Receive 1 Request,1 Response Isochronous Transmit 4 minimum,32 maximum Isochronous Receive 4 minimum,32 maximum Self-ID Receive 1 Physical Receive 0(not programmable like Physical Response those above) Each asynchronous and isochronous context is comprised of a buffer descriptor list called a DMA context program,stored in main memory.Buffers are specified within the DMA context program by DM4 descriptors.Although there are some differences from controller to controller as to how the DMA descriptors are used,all DMA descriptors use the same basic format.The DMA controller sequences through its DMA context program(s)to find the necessary data buffers.The mech- anism for sequencing through DMA contexts differs somewhat from one controller to the next and is described in detail for each type of DMA in its respective chapter. The Self-ID receive controller does not utilize a DMA context program and consists instead of a pair of registers;one to be configured by software,and one to be maintained by hardware. The 1394 Open HCI also has a physical request DMA controller that processes incoming requests that read directly from host memory.This controller does not have a DMA context,it is instead controlled by dedicated registers. 1.3.2.1 Asynchronous transmit DMA Asynchronous transmit DMA(AT DMA)utilizes three data streams,one each for AT DMA request,AT DMA response, and the Physical Response Unit.These three functions can share resources. AT DMA request and AT DMA response move transmit packets from buffers in memory to the corresponding FIFO (request transmit FIFO or response transmit FIFO).For each packet sent,it waits for the acknowledge to be returned.If the acknowledge is busy,the DMA context will resend the packet up to a software-configurable number of times for single-phase retry,or up to a software-configurable time limit for dual-phase retry.If out-of-order AT is implemented,the Host Controller can make forward progress in the context program attempting packets beyond one acknowledged with busy.The busied packets are retried according to a configurable retry limit,but not necessarily back-to-back. When the receive DMA indicates that a physical read has been received,the Physical Response Unit takes over to send the response packet.The Physical Response Unit can only interrupt the AT DMA response controller or AT DMA request controller between packets. The asynchronous transmit DMA supports either the single-phase retry protocol(retry_X)or the dual-phase retry protocol (retry_1/retry_A/retry_B).See P1394a for more information on the dual-phase retry protocol. Page 4 Copyright 1996-2000 All rights reserved
Page 4 Copyright © 1996-2000 All rights reserved. Introduction 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 1.3.2 DMA The 1394 Open HCI supports seven types of DMA. Each type of DMA has reserved register space and can support at least one distinct logical data stream referred to as a DMA context. Each asynchronous and isochronous context is comprised of a buffer descriptor list called a DMA context program, stored in main memory. Buffers are specified within the DMA context program by DMA descriptors. Although there are some differences from controller to controller as to how the DMA descriptors are used, all DMA descriptors use the same basic format. The DMA controller sequences through its DMA context program(s) to find the necessary data buffers. The mechanism for sequencing through DMA contexts differs somewhat from one controller to the next and is described in detail for each type of DMA in its respective chapter. The Self-ID receive controller does not utilize a DMA context program and consists instead of a pair of registers; one to be configured by software, and one to be maintained by hardware. The 1394 Open HCI also has a physical request DMA controller that processes incoming requests that read directly from host memory. This controller does not have a DMA context, it is instead controlled by dedicated registers. 1.3.2.1 Asynchronous transmit DMA Asynchronous transmit DMA (AT DMA) utilizes three data streams, one each for AT DMA request, AT DMA response, and the Physical Response Unit. These three functions can share resources. AT DMA request and AT DMA response move transmit packets from buffers in memory to the corresponding FIFO (request transmit FIFO or response transmit FIFO). For each packet sent, it waits for the acknowledge to be returned. If the acknowledge is busy, the DMA context will resend the packet up to a software-configurable number of times for single-phase retry, or up to a software-configurable time limit for dual-phase retry. If out-of-order AT is implemented, the Host Controller can make forward progress in the context program attempting packets beyond one acknowledged with busy. The busied packets are retried according to a configurable retry limit, but not necessarily back-to-back. When the receive DMA indicates that a physical read has been received, the Physical Response Unit takes over to send the response packet. The Physical Response Unit can only interrupt the AT DMA response controller or AT DMA request controller between packets. The asynchronous transmit DMA supports either the single-phase retry protocol (retry_X) or the dual-phase retry protocol (retry_1/retry_A/retry_B). See P1394a for more information on the dual-phase retry protocol. Table 1-1 — DMA controller types and contexts DMA controller type number of contexts Asynchronous Transmit 1 Request, 1 Response Asynchronous Receive 1 Request, 1 Response Isochronous Transmit 4 minimum, 32 maximum Isochronous Receive 4 minimum, 32 maximum Self-ID Receive 1 Physical Receive & Physical Response 0 (not programmable like those above)