Table of Contents 1394 Open Host Controller Interface Specification /Release 1.1 Printed 1/10/00 5.7.3 LPS and linkEnable.......... 49 5.8 Bus Management CSR Initialization Registers. .50 5.9 FairnessControl register (optional)..... 51 5.10 LinkControl registers(set and clear)........ 51 5.11 Node identification and status register 53 5.12 PHY control register....... 54 5.13 Isochronous Cycle Timer Register.................... 55 5.14 Asynchronous Request Filters............ 55 5.14.1 AsynchronousRequestFilter Registers(set and clear) 55 5.14.2 PhysicalRequestFilter Registers (set and clear)....... 57 5.15 Physical Upper Bound register (optional)...... 58 6.Interrupts 61 6.1 IntEvent (set and clear)................ .61 6.1.I busReset.. 64 6.2 IntMask (set and clear)..... 64 6.3 IsochTx interrupt.registers.......... 65 6.3.1 isoXmitIntEvent (set and clear).. 66 6.3.2 isoXmitIntMask (set and clear) 67 6.4 IsochRx interrupt registers....... 67 6.4.1 isoRecvIntEvent(set and clear)... 67 6.4.2 isoRecvIntMask (set and clear).... 68 7.Asynchronous Transmit DMA...... .69 7.1 AT DMA Context Programs.......... 69 7.1.1 OUTPUT_MORE descriptor.... .70 7.1.2 OUTPUT MORE Immediate descriptor .71 7.1.3 OUTPUT_LAST descriptor... 72 7.1.4 OUTPUT LAST Immediate descriptor 74 7.1.5 AT DMA descriptor usage............ 76 7.1.5.1C0 nmand.Z… 76 7.1.5.2 Command.xferStatus.... 76 7.1.5.3 Command.timeStamp............ 76 7.1.5.3.I timeStamp value for Requests...... .77 7.1.5.3.2 timeStamp value for Ping Requests 77 7.1.5.3.3 timeStamp value for Responses 77 7.2 AT DMA context registers...... 80 7.2.1 CommandPtr........ 80 7.2.2 ContextControl register (set and clear)......... 80 7.2.2.1 Writing status back to context command descriptors. 81 7.2.3 Bus Reset.… 81 7.2.3.1 Host Controller Behavior for AT........ .81 7.2.3.2 Software Guidelines............... 81 7.3 ack data_error… 82 7.4 AT Retries.… 82 7.5 Fairness...... 82 7.6 AT Interrupts. 83 7.7AT Pipelining. 83 7.8 AT Data Formats..... 84 7.8.1 Asynchronous Transmit Requests 84 7.8.1.1 No-data transmit.... .84 7.8.1.2 Quadlet transmit..... 85 Copyright1996-2000 All rights reserved Page vii
Copyright © 1996-2000 All rights reserved. Page vii Table of Contents 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 5.7.3 LPS and linkEnable..................................................................................................................................49 5.8 Bus Management CSR Initialization Registers ...................................................................................................50 5.9 FairnessControl register (optional) .....................................................................................................................51 5.10 LinkControl registers (set and clear).................................................................................................................51 5.11 Node identification and status register ..............................................................................................................53 5.12 PHY control register .........................................................................................................................................54 5.13 Isochronous Cycle Timer Register ....................................................................................................................55 5.14 Asynchronous Request Filters ..........................................................................................................................55 5.14.1 AsynchronousRequestFilter Registers (set and clear) ............................................................................55 5.14.2 PhysicalRequestFilter Registers (set and clear)......................................................................................57 5.15 Physical Upper Bound register (optional) .........................................................................................................58 6. Interrupts ..........................................................................................................................................................................61 6.1 IntEvent (set and clear) .......................................................................................................................................61 6.1.1 busReset ...................................................................................................................................................64 6.2 IntMask (set and clear) .......................................................................................................................................64 6.3 IsochTx interrupt.registers ..................................................................................................................................65 6.3.1 isoXmitIntEvent (set and clear)................................................................................................................66 6.3.2 isoXmitIntMask (set and clear) ................................................................................................................67 6.4 IsochRx interrupt registers..................................................................................................................................67 6.4.1 isoRecvIntEvent (set and clear)................................................................................................................67 6.4.2 isoRecvIntMask (set and clear) ................................................................................................................68 7. Asynchronous Transmit DMA .........................................................................................................................................69 7.1 AT DMA Context Programs ...............................................................................................................................69 7.1.1 OUTPUT_MORE descriptor....................................................................................................................70 7.1.2 OUTPUT_MORE_Immediate descriptor .................................................................................................71 7.1.3 OUTPUT_LAST descriptor .....................................................................................................................72 7.1.4 OUTPUT_LAST_Immediate descriptor ..................................................................................................74 7.1.5 AT DMA descriptor usage........................................................................................................................76 7.1.5.1 Command.Z...................................................................................................................................76 7.1.5.2 Command.xferStatus .....................................................................................................................76 7.1.5.3 Command.timeStamp ....................................................................................................................76 7.1.5.3.1 timeStamp value for Requests.............................................................................................77 7.1.5.3.2 timeStamp value for Ping Requests ....................................................................................77 7.1.5.3.3 timeStamp value for Responses ..........................................................................................77 7.2 AT DMA context registers ..................................................................................................................................80 7.2.1 CommandPtr ............................................................................................................................................80 7.2.2 ContextControl register (set and clear).....................................................................................................80 7.2.2.1 Writing status back to context command descriptors ....................................................................81 7.2.3 Bus Reset .................................................................................................................................................81 7.2.3.1 Host Controller Behavior for AT ...................................................................................................81 7.2.3.2 Software Guidelines ......................................................................................................................81 7.3 ack_data_error ....................................................................................................................................................82 7.4 AT Retries...........................................................................................................................................................82 7.5 Fairness...............................................................................................................................................................82 7.6 AT Interrupts.......................................................................................................................................................83 7.7 AT Pipelining......................................................................................................................................................83 7.8 AT Data Formats.................................................................................................................................................84 7.8.1 Asynchronous Transmit Requests ............................................................................................................84 7.8.1.1 No-data transmit............................................................................................................................84 7.8.1.2 Quadlet transmit ............................................................................................................................85
Table of Contents 1394 Open Host Controller Interface Specification Release 1.1 Printed 1/10/00 7.8.1.3 Block transmit....... 87 7.8.1.4 PHY packet transmit. 7.8.2 Asynchronous Transmit Responses.... 89 89 7.8.2.1 No-data transmit. 89 7.8.2.2 Quadlet transmit. 90 7.8.2.3 Block transmit... .91 7.8.3 Asynchronous Transmit Streams 93 8.Asynchronous Receive DMA.................. 95 8.1 AR DMA Context Programs............ 095 8.1.1 INPUT_MORE descriptor........... 95 8.1.2 AR DMA descriptor usage............. .96 8.2 bufferFill mode........ .97 8.3 Asynchronous Receive Context Registers.............. 97 8.3.1AR DMA Commandptr register9 8.3.2 AR ContextControl register(set and clear)... .98 8.4 AR DMA Controller.. .98 8.4.1 Asynchronous Filter Registers... 98 8.4.2 AR DMA Controller processing. .99 8.4.2.1 AR DMA Packet Trailer ,100 8.4.2.2 Error Handling......... .100 8.4.2.3 Bus Reset Packet...... 101 8.5 PHY Packets.… …102 8.6 Asynchronous Receive Interrupts...... .102 8.7 Asynchronous Receive Data Formats........ .103 8.7.1 Asynchronous Receive Requests............... .104 8.7.1.1 No-data receive......... .104 8.7.1.2 Quadlet Receive......... ,104 8.7.1.3 Block receive..... ,106 8.7.1.4 PHY packet receive.... 107 8.7.2 Asynchronous Receive Responses 108 8.7.2.1 No-data receive..... .108 8.7.2.2 Quadlet Receive ,108 8.7.2.3 Block receive........... .109 9.Isochronous Transmit DMA........ .111 9.1 IT DMA Context Programs.......... .111 9.1.1 IT DMA command descriptor overview.... .111 9.1.2 OUTPUT MORE descriptor... .112 9.1.3 OUTPUT MORE-Immediate descriptor. .113 9.1.4 OUTPUT LAST descriptor................. 114 9.1.5 OUTPUT LAST-Immediate descriptor... .115 9.1.6 STORE VALUE descriptor.. .116 9.1.7 IT DMA descriptor usage.......... ..117 9.2 IT Context Registers. .118 9.2.1C0 mmandPtr............. ...118 9.2.2 IT ContextControl Register.... ,119 9.3 Isochronous transmit DMA controller..... ..120 9.3.1 IT DMA Processing............ ,121 9.3.2 Prefetching IT Packets.... .122 9.3.3 Isochronous Transmit Cycle Loss .122 9.3.4 Skip Processing Overflow 123 Page viii Copyright 1996-2000 All rights reserved
Page viii Copyright © 1996-2000 All rights reserved. Table of Contents 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 7.8.1.3 Block transmit ...............................................................................................................................87 7.8.1.4 PHY packet transmit .....................................................................................................................89 7.8.2 Asynchronous Transmit Responses..........................................................................................................89 7.8.2.1 No-data transmit............................................................................................................................89 7.8.2.2 Quadlet transmit ............................................................................................................................90 7.8.2.3 Block transmit ...............................................................................................................................91 7.8.3 Asynchronous Transmit Streams..............................................................................................................93 8. Asynchronous Receive DMA ...........................................................................................................................................95 8.1 AR DMA Context Programs...............................................................................................................................95 8.1.1 INPUT_MORE descriptor........................................................................................................................95 8.1.2 AR DMA descriptor usage.......................................................................................................................96 8.2 bufferFill mode ...................................................................................................................................................97 8.3 Asynchronous Receive Context Registers...........................................................................................................97 8.3.1 AR DMA CommandPtr register...............................................................................................................97 8.3.2 AR ContextControl register (set and clear) ..............................................................................................98 8.4 AR DMA Controller ...........................................................................................................................................98 8.4.1 Asynchronous Filter Registers .................................................................................................................98 8.4.2 AR DMA Controller processing ..............................................................................................................99 8.4.2.1 AR DMA Packet Trailer ..............................................................................................................100 8.4.2.2 Error Handling ............................................................................................................................100 8.4.2.3 Bus Reset Packet .........................................................................................................................101 8.5 PHY Packets .....................................................................................................................................................102 8.6 Asynchronous Receive Interrupts .....................................................................................................................102 8.7 Asynchronous Receive Data Formats ...............................................................................................................103 8.7.1 Asynchronous Receive Requests............................................................................................................104 8.7.1.1 No-data receive............................................................................................................................104 8.7.1.2 Quadlet Receive ..........................................................................................................................104 8.7.1.3 Block receive...............................................................................................................................106 8.7.1.4 PHY packet receive .....................................................................................................................107 8.7.2 Asynchronous Receive Responses .........................................................................................................108 8.7.2.1 No-data receive............................................................................................................................108 8.7.2.2 Quadlet Receive ..........................................................................................................................108 8.7.2.3 Block receive...............................................................................................................................109 9. Isochronous Transmit DMA...........................................................................................................................................111 9.1 IT DMA Context Programs ..............................................................................................................................111 9.1.1 IT DMA command descriptor overview.................................................................................................111 9.1.2 OUTPUT_MORE descriptor..................................................................................................................112 9.1.3 OUTPUT_MORE-Immediate descriptor................................................................................................113 9.1.4 OUTPUT_LAST descriptor ...................................................................................................................114 9.1.5 OUTPUT_LAST-Immediate descriptor .................................................................................................115 9.1.6 STORE_VALUE descriptor ...................................................................................................................116 9.1.7 IT DMA descriptor usage.......................................................................................................................117 9.2 IT Context Registers .........................................................................................................................................118 9.2.1 CommandPtr ..........................................................................................................................................118 9.2.2 IT ContextControl Register....................................................................................................................119 9.3 Isochronous transmit DMA controller ..............................................................................................................120 9.3.1 IT DMA Processing ...............................................................................................................................121 9.3.2 Prefetching IT Packets ...........................................................................................................................122 9.3.3 Isochronous Transmit Cycle Loss ..........................................................................................................122 9.3.4 Skip Processing Overflow......................................................................................................................123
Table of Contents 1394 Open Host Controller Interface Specification /Release 1.1 Printed 1/10/00 9.3.5 FIFO Underrun............. 124 9.3.6 Determining the number of implemented IT DMA contexts.........................................125 9.4 Appending to an IT DMA Context Program.. 125 9.5 IT Interrupts.… 125 9.5.1 cyclelnconsistent Interrupt 125 9.5.2 busReset Interrupt..... 125 9.5.3 UnrecoverableError Interrupt 126 9.61 T Data Format.… 126 10.Isochronous Receive DMA 129 10.1 IR DMA Context Programs............. .129 10.1.1 Buffer-Fill and Packet-per-Buffer Descriptors 129 10.1.2 Dual-Buffer Descriptor.... 130 10.1.3 Descriptor Z Values...... 132 10.2 Receive Modes. 133 10.2.1 Buffer Fill Mode... 133 10.2.2 Packet-per-Buffer Mode.. 134 10.2.2.1 Command.xferStatus and Command.resCount updates.... 135 10.2.3 Dual-Buffer Mode...... 135 10.3 IR Context Registers. 137 10.3.1 CommandPtr ...... 137 10.3.2 IR ContextControl register (set and clear)............ 137 10.3.3 Isochronous receive contextMatch register.................. 140 10.4 Isochronous receive DMA controller141 10.4.1 Isochronous receive multi-channel support................ 141 10.4.1.1 IRMultiChanMask registers (set and clear) 141 10.4.2 Isochronous receive single-channel support........ 142 10.4.3 Duplicate channels.. 142 10.4.4 Determining the number of implemented IR DMA contexts. 143 10.5 IR Interrupts… 143 10.5.1 cyclelnconsistent Interrupt. 143 10.5.2 busReset Interrupt 143 l0.6 IR Data Formats.................. 143 10.6.1 bufferFill mode formats................ 144 10.6.1.1 IR with header/trailer..... 144 10.6.1.2 IR without header/trailer 145 10.6.2 Packet-per-buffer mode and dual-buffer mode formats 145 10.6.2.1 IR with header/trailer.... 145 10.6.2.2 IR without header/trailer 146 11.Self ID Receive .147 11.1 Self ID Buffer Pointer Register........... .147 11.2 Self ID Count Register............ 147 11.3 Self-ID receive.......... 148 11.4 Enabling the SelfID DMA........ .149 11.5 Interrupt Considerations for SelflD DMA 149 11.6 SelflDs Received Outside of Bus Initialization 149 12.Physical Requests..... 151 12.1 Filtering Physical Requests. .152 12.2 Posted Writes......... .152 Copyright1996-2000 All rights reserved Pageix
Copyright © 1996-2000 All rights reserved. Page ix Table of Contents 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 9.3.5 FIFO Underrun.......................................................................................................................................124 9.3.6 Determining the number of implemented IT DMA contexts..................................................................125 9.4 Appending to an IT DMA Context Program.....................................................................................................125 9.5 IT Interrupts......................................................................................................................................................125 9.5.1 cycleInconsistent Interrupt .....................................................................................................................125 9.5.2 busReset Interrupt ..................................................................................................................................125 9.5.3 UnrecoverableError Interrupt .................................................................................................................126 9.6 IT Data Format .................................................................................................................................................126 10. Isochronous Receive DMA ..........................................................................................................................................129 10.1 IR DMA Context Programs ............................................................................................................................129 10.1.1 Buffer-Fill and Packet-per-Buffer Descriptors .....................................................................................129 10.1.2 Dual-Buffer Descriptor ........................................................................................................................130 10.1.3 Descriptor Z Values..............................................................................................................................132 10.2 Receive Modes................................................................................................................................................133 10.2.1 Buffer Fill Mode ..................................................................................................................................133 10.2.2 Packet-per-Buffer Mode.......................................................................................................................134 10.2.2.1 Command.xferStatus and Command.resCount updates .............................................................135 10.2.3 Dual-Buffer Mode................................................................................................................................135 10.3 IR Context Registers.......................................................................................................................................137 10.3.1 CommandPtr ........................................................................................................................................137 10.3.2 IR ContextControl register (set and clear)............................................................................................137 10.3.3 Isochronous receive contextMatch register ..........................................................................................140 10.4 Isochronous receive DMA controller ..............................................................................................................141 10.4.1 Isochronous receive multi-channel support ..........................................................................................141 10.4.1.1 IRMultiChanMask registers (set and clear) ...............................................................................141 10.4.2 Isochronous receive single-channel support .........................................................................................142 10.4.3 Duplicate channels ...............................................................................................................................142 10.4.4 Determining the number of implemented IR DMA contexts................................................................143 10.5 IR Interrupts....................................................................................................................................................143 10.5.1 cycleInconsistent Interrupt ...................................................................................................................143 10.5.2 busReset Interrupt ................................................................................................................................143 10.6 IR Data Formats..............................................................................................................................................143 10.6.1 bufferFill mode formats .......................................................................................................................144 10.6.1.1 IR with header/trailer.................................................................................................................144 10.6.1.2 IR without header/trailer ...........................................................................................................145 10.6.2 Packet-per-buffer mode and dual-buffer mode formats ........................................................................145 10.6.2.1 IR with header/trailer.................................................................................................................145 10.6.2.2 IR without header/trailer ...........................................................................................................146 11. Self ID Receive ............................................................................................................................................................147 11.1 Self ID Buffer Pointer Register.......................................................................................................................147 11.2 Self ID Count Register....................................................................................................................................147 11.3 Self-ID receive................................................................................................................................................148 11.4 Enabling the SelfID DMA ..............................................................................................................................149 11.5 Interrupt Considerations for SelfID DMA ......................................................................................................149 11.6 SelfIDs Received Outside of Bus Initialization...............................................................................................149 12. Physical Requests.........................................................................................................................................................151 12.1 Filtering Physical Requests.............................................................................................................................152 12.2 Posted Writes..................................................................................................................................................152
Table of Contents 1394 Open Host Controller Interface Specification Release 1.1 Printed 1/10/00 12.3 Physical Responses..... 152 12.4 Physical Response Retries...... .152 12.5 Interrupt Considerations for Physical Requests 152 12.6 Bus Reset. 152 13.Host Bus Errors...... 153 13.1 Causes of Host Bus Errors....... .153 13.2 Host Controller Actions When Host Bus Error Occurs 153 13.2.1 Descriptor Read Error 153 13.2.2 xferStatus Write Error. 153 13.2.3 Transmit Data Read Error.................. .154 13.2.4 Isochronous Transmit Data Write Error................ .154 13.2.5 Asynchronous Receive DMA Data Write Error... 154 13.2.6 Isochronous Receive Data Write Error.................... 154 13.2.7physical Read Error.155 13.2.8 Physical Posted Write Error.... 155 13.2.8.1 PostedWriteAddress Register(optional) .156 13.2.8.2 Queue Rules. 157 Annex A.PCI Interface (optional)........... 159 A.1 PCI Configuration Space............ 159 A.2 Busmastering Requirements......... ,159 A.3 PCI Configuration Space for 1394 Open HCI With PCI Interface.... .159 A.3.1 COMMAND Register 160 A.32STATUS Register.........................161 A.3.3 CLASS CODE Register .161 A.3.4 Revision ID Register..... .16] A.3.5 Base Adr o Register............... .161 A.3.6 CAP PTR Register.... 162 A.3.7 PCI_HCI_Control Register 163 A.3.8 PCI Power Management Register Interface........... .163 A.3.8.1 Capability ID Register .163 A.3.8.2 Next Item Pointer Register(Nxt_Ptr)....... ,163 A.3.8.3 Power Management Capabilities Register(PMC) .164 A.3.8.4 Power Management Control/Status(PMCSR)....... ,165 A.3.8.5 PMCSR BSE.................. ,165 A.3.8.6 PM DATA... 165 A.4 PCI Power Management Behavior 166 A.4.1 Power State Transitions. 166 A.4.2 Power State Definitions. 167 A.4.3 PCI PME#Signal................. 168 A.5 PCI Expansion ROM for 1394 Open HCI........... .169 A.6 PCIBus Errors. ...169 Annex B.Summary of Register Reset Values (Informative)........... . ,171 Annex C.Summary of Bus Reset Behavior(Informative) 177 C.10 verview… .177 C.2 Asynchronous Transmit:Request Response .177 C.3 Asynchronous Receive:Request Response. .177 C.4 Isochronous Transmit .177 Page x Copyright 1996-2000 All rights reserved
Page x Copyright © 1996-2000 All rights reserved. Table of Contents 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 12.3 Physical Responses.........................................................................................................................................152 12.4 Physical Response Retries ..............................................................................................................................152 12.5 Interrupt Considerations for Physical Requests ..............................................................................................152 12.6 Bus Reset........................................................................................................................................................152 13. Host Bus Errors............................................................................................................................................................153 13.1 Causes of Host Bus Errors ..............................................................................................................................153 13.2 Host Controller Actions When Host Bus Error Occurs...................................................................................153 13.2.1 Descriptor Read Error ..........................................................................................................................153 13.2.2 xferStatus Write Error..........................................................................................................................153 13.2.3 Transmit Data Read Error ....................................................................................................................154 13.2.4 Isochronous Transmit Data Write Error ...............................................................................................154 13.2.5 Asynchronous Receive DMA Data Write Error ...................................................................................154 13.2.6 Isochronous Receive Data Write Error.................................................................................................154 13.2.7 Physical Read Error .............................................................................................................................155 13.2.8 Physical Posted Write Error .................................................................................................................155 13.2.8.1 PostedWriteAddress Register (optional) ...................................................................................156 13.2.8.2 Queue Rules ..............................................................................................................................157 Annex A. PCI Interface (optional) .....................................................................................................................................159 A.1 PCI Configuration Space .................................................................................................................................159 A.2 Busmastering Requirements ............................................................................................................................159 A.3 PCI Configuration Space for 1394 Open HCI With PCI Interface ...................................................................159 A.3.1 COMMAND Register ...........................................................................................................................160 A.3.2 STATUS Register ..................................................................................................................................161 A.3.3 CLASS_CODE Register .......................................................................................................................161 A.3.4 Revision_ID Register ............................................................................................................................161 A.3.5 Base_Adr_0 Register ............................................................................................................................161 A.3.6 CAP_PTR Register ...............................................................................................................................162 A.3.7 PCI_HCI_Control Register ...................................................................................................................163 A.3.8 PCI Power Management Register Interface...........................................................................................163 A.3.8.1 Capability ID Register ................................................................................................................163 A.3.8.2 Next Item Pointer Register (Nxt_Ptr) .........................................................................................163 A.3.8.3 Power Management Capabilities Register (PMC) ......................................................................164 A.3.8.4 Power Management Control/Status (PMCSR)............................................................................165 A.3.8.5 PMCSR_BSE .............................................................................................................................165 A.3.8.6 PM_DATA ..................................................................................................................................165 A.4 PCI Power Management Behavior ...................................................................................................................166 A.4.1 Power State Transitions.........................................................................................................................166 A.4.2 Power State Definitions.........................................................................................................................167 A.4.3 PCI PME# Signal ..................................................................................................................................168 A.5 PCI Expansion ROM for 1394 Open HCI........................................................................................................169 A.6 PCI Bus Errors.................................................................................................................................................169 Annex B. Summary of Register Reset Values (Informative) ..............................................................................................171 Annex C. Summary of Bus Reset Behavior (Informative) .................................................................................................177 C.1 Overview..........................................................................................................................................................177 C.2 Asynchronous Transmit: Request & Response ................................................................................................177 C.3 Asynchronous Receive: Request & Response ..................................................................................................177 C.4 Isochronous Transmit.......................................................................................................................................177
Table of Contents 1394 Open Host Controller Interface Specification /Release 1.1 Printed 1/10/00 C.5 Isochronous Receive............177 C.6 Self ID Receive...78 C.7 Physical Requests/Responses........... 178 C.7.Iphysical Response. 178 C.7.2 Physical Requests. 178 C.8 Control Registers....... 178 Annex D.IT DMA Supplement (Informative).............. .179 D.1 IT DMA Behavior.… 179 D.2 IT DMA Flowchart Summary............. .179 D.3 DMA-side IT DMA flowchart............. .179 D.3.1 DMA-side top half.... 181 D.3.2 DMA-side bottom half 181 D.4 Link-side IT DMA flowchart.............. 182 D.4.1 Link-side top half...... 182 D.4.2 Link-side bottom half. 184 Annex E.Sample IT DMA Controller Implementation(Informative) 185 Annex F.Extended Config ROM Entries......... 191 F.1 Mini-ROM Data Format........... 191 Copyright1996-2000 All rights reserved. Pagexi
Copyright © 1996-2000 All rights reserved. Page xi Table of Contents 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 C.5 Isochronous Receive ........................................................................................................................................177 C.6 Self ID Receive ................................................................................................................................................178 C.7 Physical Requests/Responses ...........................................................................................................................178 C.7.1 Physical Response .................................................................................................................................178 C.7.2 Physical Requests ..................................................................................................................................178 C.8 Control Registers .............................................................................................................................................178 Annex D. IT DMA Supplement (Informative) ..................................................................................................................179 D.1 IT DMA Behavior............................................................................................................................................179 D.2 IT DMA Flowchart Summary .........................................................................................................................179 D.3 DMA-side IT DMA flowchart ........................................................................................................................179 D.3.1 DMA-side top half ...............................................................................................................................181 D.3.2 DMA-side bottom half ..........................................................................................................................181 D.4 Link-side IT DMA flowchart ...........................................................................................................................182 D.4.1 Link-side top half ..................................................................................................................................182 D.4.2 Link-side bottom half ............................................................................................................................184 Annex E. Sample IT DMA Controller Implementation (Informative)................................................................................185 Annex F. Extended Config ROM Entries ...........................................................................................................................191 F.1 Mini-ROM Data Format....................................................................................................................................191