ACP ACCELERATED GRAPHICS PORT Accelerated Graphics Port Interface Specification Revision 2.0 Intel Corporation May4,1998 Intel may have patents and/or patent applications related to the various Accelerated Graphics Port(AGP or A.G.P.).interfaces described in the Accelerated Graphics Port Interface Specification.A reciprocal, royalty-free license to the electrical interfaces and bus protocols described in,and required by,the Accelerated Graphics Port Interface Specification Revision 2.0 is available from Intel
Accelerated Graphics Port Interface Specification Revision 2.0 Intel Corporation May 4, 1998 Intel may have patents and/or patent applications related to the various Accelerated Graphics Port (AGP or A.G.P.). interfaces described in the Accelerated Graphics Port Interface Specification. A reciprocal, royalty-free license to the electrical interfaces and bus protocols described in, and required by, the Accelerated Graphics Port Interface Specification Revision 2.0 is available from Intel
Revision 2.0 Accelerated Graphics Port Interface Specification Copyright Intel Corporation 1996-1998 All rights reserved. THIS SPECIFICATION IS PROVIDEDAS IS"WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY,FITNESS FOR ANY PARTICULAR PURPOSE OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL,SPECIFICATION,OR SAMPLE.NO LICENSE,EXPRESS OR IMPLIED,BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED OR INTENDED HEREBY INTEL DISCLAIMS ALL LIABILITY INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTSRELATING TO USE OF INFORMATION IN THIS SPECIFICATION INTEL DOES NOT WARRANT OR REPRESENT THAT SUCH USE WILL NOT INFRINGE SUCH RIGHTS *THIRD-PARTY BRANDS AND NAMES ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS 2
Revision 2.0 2 Accelerated Graphics Port Interface Specification Copyright © Intel Corporation 1996-1998 All rights reserved. THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION , OR SAMPLE. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED OR INTENDED HEREBY. INTEL DISCLAIMS ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OF INFORMATION IN THIS SPECIFICATION. INTEL DOES NOT WARRANT OR REPRESENT THAT SUCH USE WILL NOT INFRINGE SUCH RIGHTS. *THIRD-PARTY BRANDS AND NAMES ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS
Revision 2.0 Contents 1.Introduction. .19 1.I Motivation 19 1.2 Relationship to PCI. .20 1.3 Terminology....... .21 2.Architectural Context and Scope...... .23 2.1 Two Usage Models:“Execute”and"DMA” .23 2.2 Queuing Models........ 24 2.3 Performance Considerations...... .26 2.4 Platform Dependencies........ .27 3.Signals and Protocol Specification..... 31 3.1 Pin Description. .31 3.1.1 Semantics of PCI Signals............ 36 3.1.2 Configuration of an A.G.P.Master.... 40 3.1.2.1 Device for A.G.P.Only Operation........... 40 3.1.2.2 Device for Both PCI and A.G.P.Operation 40 3.2 Operation Overview. 3.2.1 Pipeline Operation.. .41 3.2.2 Addressing Modes and Bus Operations 43 3.3 Bus Commands... 44 3.4 Access Ordering Rules. 46 3.4.1 Ordering Rules and Implications.... 46 3.4.2 Deadlock Avoidance............ .50 3.4.3 Flush and Fence Commands. 50 3.4.4 Access Request Priority.............. 51 3.5 Bus Transactions....... 52 3.5.1 Enqueueing Requests............ .52 3.5.1.1 Address Demultiplexing Option 52 3.5.1.2 AD Bus.......... .57 3.5.1.3 64-bit Requests on the AD Bus. 59 3.5.2 Flow Control. 61 3
Revision 2.0 3 Contents 1. Introduction..............................................................................................................................19 1.1 Motivation ......................................................................................................................................................... 19 1.2 Relationship to PCI............................................................................................................................................ 20 1.3 Terminology ...................................................................................................................................................... 21 2. Architectural Context and Scope ...........................................................................................23 2.1 Two Usage Models: “Execute” and “DMA” .................................................................................................... 23 2.2 Queuing Models ................................................................................................................................................ 24 2.3 Performance Considerations.............................................................................................................................. 26 2.4 Platform Dependencies...................................................................................................................................... 27 3. Signals and Protocol Specification .........................................................................................31 3.1 Pin Description .................................................................................................................................................. 31 3.1.1 Semantics of PCI Signals............................................................................................................................ 36 3.1.2 Configuration of an A.G.P. Master............................................................................................................. 40 3.1.2.1 Device for A.G.P. Only Operation ...................................................................................................... 40 3.1.2.2 Device for Both PCI and A.G.P. Operation......................................................................................... 40 3.2 Operation Overview .......................................................................................................................................... 41 3.2.1 Pipeline Operation ...................................................................................................................................... 41 3.2.2 Addressing Modes and Bus Operations...................................................................................................... 43 3.3 Bus Commands.................................................................................................................................................. 44 3.4 Access Ordering Rules ...................................................................................................................................... 46 3.4.1 Ordering Rules and Implications ................................................................................................................ 46 3.4.2 Deadlock Avoidance .................................................................................................................................. 50 3.4.3 Flush and Fence Commands....................................................................................................................... 50 3.4.4 Access Request Priority.............................................................................................................................. 51 3.5 Bus Transactions ............................................................................................................................................... 52 3.5.1 Enqueueing Requests.................................................................................................................................. 52 3.5.1.1 Address Demultiplexing Option .......................................................................................................... 52 3.5.1.2 AD Bus ................................................................................................................................................ 57 3.5.1.3 64-bit Requests on the AD Bus............................................................................................................ 59 3.5.2 Flow Control............................................................................................................................................... 61
Revision 2.0 3.5.2.1 Address Flow Control....... .61 3.5.2.2 Data Flow Control..... 61 3.5.2.2.1 Read Flow Control. 64 3.5.2.2.2 Write Data Flow Control... 69 3.5.2.3 Other Flow Control Rules. 71 3.5.3 Data Transactions........... 72 3.5.3.1 1x Data Transfers............... 72 3.5.3.2 2x Data Transfers............ 75 3.5.3.3 Relationship Between xRDY#and AD_STBx 78 3.5.3.4 4x Data Transfers ...................... .79 3.5.3.5 Fast Write Transfers.......... 83 3.5.3.5.1 FW Basic Transaction................. 85 3.5.3.5.1.1 FW Transactions with Waitstates. 87 3.5.3.5.2 FW Transaction with Different Terminations 89 3.5.3.5.2.1Rety 89 3.5.3.5.2.2 Disconnect With Data.......... ””””c-r-r-r* 89 3.5.3.5.2.3 Disconnect Without Data 90 3.5.3.5.2.4 Target-Abort... 92 3.5.3.5.2.5 Master-Abort............ 93 3.5.3.5.2.6 Normal. 94 3.5.3.5.3 Back to Back Transactions......... 94 3.5.3.5.3.1FWt0FW 96 3.5.3.5.3.1.1 Write Buffer Full.... 98 3.5.3.5.3.1.2 DEVSEL#Operation and FW Transactions 100 3.5.3.5.3.2 FW to PCI.Read....... 103 3.5.3.5.3.3 PCIe Read to FW.............. 104 3.5.3.5.3.4 FW to A.G.P.Read............. 105 3.5.3.5.3.5 A.G.P.Read to FW.............. 108 3.5.3.5.3.6 FW to A.G.P.Write.............. 109 3.5.3.5.3.7A.G.P.Write Followed by FW................ 111 3.5.3.5.3.8 FW Followed by Graphics PCI Master Read 112 3.5.3.5.3.9 Graphics PCI Master Read Followed by FW.... 113 3.5.3.5.3.10FW Followed by Graphics PCI Master Write......114 4
Revision 2.0 4 3.5.2.1 Address Flow Control.......................................................................................................................... 61 3.5.2.2 Data Flow Control ............................................................................................................................... 61 3.5.2.2.1 Read Flow Control........................................................................................................................ 64 3.5.2.2.2 Write Data Flow Control .............................................................................................................. 69 3.5.2.3 Other Flow Control Rules.................................................................................................................... 71 3.5.3 Data Transactions ....................................................................................................................................... 72 3.5.3.1 1x Data Transfers ................................................................................................................................ 72 3.5.3.2 2x Data Transfers ................................................................................................................................ 75 3.5.3.3 Relationship Between xRDY# and AD_STBx .................................................................................... 78 3.5.3.4 4x Data Transfers ................................................................................................................................ 79 3.5.3.5 Fast Write Transfers ............................................................................................................................ 83 3.5.3.5.1 FW Basic Transaction .................................................................................................................. 85 3.5.3.5.1.1 FW Transactions with Waitstates .......................................................................................... 87 3.5.3.5.2 FW Transaction with Different Terminations............................................................................... 89 3.5.3.5.2.1 Retry ...................................................................................................................................... 89 3.5.3.5.2.2 Disconnect With Data............................................................................................................ 89 3.5.3.5.2.3 Disconnect Without Data....................................................................................................... 90 3.5.3.5.2.4 Target-Abort .......................................................................................................................... 92 3.5.3.5.2.5 Master-Abort ......................................................................................................................... 93 3.5.3.5.2.6 Normal................................................................................................................................... 94 3.5.3.5.3 Back to Back Transactions ........................................................................................................... 94 3.5.3.5.3.1 FW to FW .............................................................................................................................. 96 3.5.3.5.3.1.1 Write Buffer Full ............................................................................................................ 98 3.5.3.5.3.1.2 DEVSEL# Operation and FW Transactions ................................................................. 100 3.5.3.5.3.2 FW to PCI c Read ................................................................................................................. 103 3.5.3.5.3.3 PCIc Read to FW ................................................................................................................. 104 3.5.3.5.3.4 FW to A.G.P. Read .............................................................................................................. 105 3.5.3.5.3.5 A.G.P. Read to FW .............................................................................................................. 108 3.5.3.5.3.6 FW to A.G.P. Write ............................................................................................................. 109 3.5.3.5.3.7 A.G.P. Write Followed by FW ............................................................................................ 111 3.5.3.5.3.8 FW Followed by Graphics PCI Master Read ...................................................................... 112 3.5.3.5.3.9 Graphics PCI Master Read Followed by FW ...................................................................... 113 3.5.3.5.3.10 FW Followed by Graphics PCI Master Write.................................................................... 114
Revision 2.0 3.5.3.5.3.11 Graphics PCI Master Write Followed by FW. .115 3.5.3.5.3.12 FW Followed by PIPE#....... .116 3.5.3.5.3.13 PIPE#Followed by FW....... .117 3.5.3.5.3.13.1 PIPE#Followed by FW with Delay. .118 3.6 Arbitration....... 119 3.6.1 Introduction....... 119 3.6.2 Master's REQ#Signal. 119 3.6.3 GNT#and ST[2::0]................ 120 3.6.4A.G.P.Master.… 120 3.6.4.1 A.G.P.Master Initiating an A.G.P.Request. 120 3.6.4.2 A.G.P.Master Initiating a PCI Transaction 122 3.6.5A.G.P.Arbiter… 123 3.6.6 GNT#Pipelining 124 3.6.6.1 Pipelining GNT#s............ 126 3.6.6.2 A Request Transaction Followed by a Request Transaction.. 127 3.6.6.3 A Request Transaction Followed by a Data Transfer............................ 132 3.6.6.4 A Data Transfer Followed by a Request...... 139 3.6.6.5 A Data Transfer Followed by a Data Transfer.. 146 3.7 Error Rep0 rting.… 153 3.8 Special Design Considerations... 153 4.Electrical Specification.......... .155 4.1Overview. 155 4.1.1 Introduction..... 155 4.1.2 Transfer Mode Operation......... 155 4.1.2.1 Transfer Mode Signaling Levels. 155 4.1.2.2 1x Transfer Mode Operation.... 156 4.1.2.3 2x Transfer Mode Operation..... 156 4.1.2.4 4x Transfer Mode Operation....... 156 4.1.2.5 2x/4x Timing Model......... 156 4.1.2.6 Transmit/Receive Outer Loop...... 158 4.1.2.7 Transmit to Receive Inner loop 158 4.1.2.8 Transmit Outer to Inner Loop.... 159 4.1.2.9 Receive Inner to Outer Loop. 161 5
Revision 2.0 5 3.5.3.5.3.11 Graphics PCI Master Write Followed by FW.................................................................... 115 3.5.3.5.3.12 FW Followed by PIPE# ..................................................................................................... 116 3.5.3.5.3.13 PIPE# Followed by FW ..................................................................................................... 117 3.5.3.5.3.13.1 PIPE# Followed by FW with Delay............................................................................ 118 3.6 Arbitration ....................................................................................................................................................... 119 3.6.1 Introduction .............................................................................................................................................. 119 3.6.2 Master’s REQ# Signal .............................................................................................................................. 119 3.6.3 GNT# and ST[2::0] .................................................................................................................................. 120 3.6.4 A.G.P. Master ........................................................................................................................................... 120 3.6.4.1 A.G.P. Master Initiating an A.G.P. Request. ..................................................................................... 120 3.6.4.2 A.G.P. Master Initiating a PCI Transaction ....................................................................................... 122 3.6.5 A.G.P. Arbiter .......................................................................................................................................... 123 3.6.6 GNT# Pipelining ...................................................................................................................................... 124 3.6.6.1 Pipelining GNT#s .............................................................................................................................. 126 3.6.6.2 A Request Transaction Followed by a Request Transaction.............................................................. 127 3.6.6.3 A Request Transaction Followed by a Data Transfer. ....................................................................... 132 3.6.6.4 A Data Transfer Followed by a Request............................................................................................ 139 3.6.6.5 A Data Transfer Followed by a Data Transfer................................................................................... 146 3.7 Error Reporting................................................................................................................................................ 153 3.8 Special Design Considerations ........................................................................................................................ 153 4. Electrical Specification ..........................................................................................................155 4.1 Overview ......................................................................................................................................................... 155 4.1.1 Introduction .............................................................................................................................................. 155 4.1.2 Transfer Mode Operation ......................................................................................................................... 155 4.1.2.1 Transfer Mode Signaling Levels........................................................................................................ 155 4.1.2.2 1x Transfer Mode Operation ............................................................................................................. 156 4.1.2.3 2x Transfer Mode Operation ............................................................................................................. 156 4.1.2.4 4x Transfer Mode Operation ............................................................................................................. 156 4.1.2.5 2x/4x Timing Model.......................................................................................................................... 156 4.1.2.6 Transmit/Receive Outer Loop ........................................................................................................... 158 4.1.2.7 Transmit to Receive Inner loop ......................................................................................................... 158 4.1.2.8 Transmit Outer to Inner Loop............................................................................................................ 159 4.1.2.9 Receive Inner to Outer Loop ............................................................................................................. 161