Preface This preface introduces the ARM Cortex"-M4 Processor Technical Reference Mamual It contains the following: About this book on age 7. ·Feedback on page0 ARM100166_0001_00_en Copygh1gsve 6
Preface This preface introduces the ARM® Cortex® -M4 Processor Technical Reference Manual. It contains the following: • About this book on page 7. • Feedback on page 10. ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 6 Non-Confidential
About this ook About this book ARM Cortex-M4 Technical Reference Manual(TRM).This manual contains documentation for the Cmd.nmn Product revision status Identifies the major revision of the product,for example,rl. pn Identifies the minor revision or modification status of the product,for example,p2. Intended audience program Using this book This book is organized into the following chapters Chapter 1 Introduction This chapter in roduces the Cortex-M4 processor and instruction set,processor features and interfaces,configurable options,and product documentation. Chapter 2 Functional Description This chapter introduces the Cortex-M4 processor and its external interfaces. the Co ortex-M4 processor programmers'model. Chapter 4 System Control Chapter 5 Memory Protection Unit This chapter describes the processor Memory Protection Unit(MPU). interrupt handling,and controls power management. e programmers'model of the Floating-Point Unit (FPU). Chapter 8 Debug This chapter describes how to debug and test software running on the processor Chapter 11 Trace Port Interface Unit This chapter describes the Cortex-M4 TPIU,the Trace Port Interface Unit that is specific to the Cortex-M4 processor. ARM100166000100en opygh1ghtsv
About this book ARM Cortex-M4 Technical Reference Manual (TRM). This manual contains documentation for the Cortex-M4 processor, the programmer’s model, instruction set, registers, memory map,floating point, multimedia, trace and debug support. Product revision status The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2, where: rm Identifies the major revision of the product, for example, r1. pn Identifies the minor revision or modification status of the product, for example, p2. Intended audience This manual is written to help system designers, system integrators, verification engineers, and software programmers who are implementing a System-on-Chip (SoC) device based on the Cortex® -M4 processor. Using this book This book is organized into the following chapters: Chapter 1 Introduction This chapter introduces the Cortex-M4 processor and instruction set, processor features and interfaces, configurable options, and product documentation. Chapter 2 Functional Description This chapter introduces the Cortex-M4 processor and its external interfaces. Chapter 3 Programmers’ Model This chapter describes the Cortex-M4 processor programmers’ model. Chapter 4 System Control This chapter provides a summary of the system control registers whose implementation is specific to the Cortex-M4 processor. Chapter 5 Memory Protection Unit This chapter describes the processor Memory Protection Unit (MPU). Chapter 6 Nested Vectored Interrupt Controller This chapter describes the Nested Vectored Interrupt Controller (NVIC). The NVIC provides configurable interrupt handling abilities to the processor, facilitates low- latency exception and interrupt handling, and controls power management. Chapter 7 Floating-Point Unit This chapter describes the programmers’ model of the Floating-Point Unit (FPU). Chapter 8 Debug This chapter describes how to debug and test software running on the processor. Chapter 9 Data Watchpoint and Trace Unit This chapter describes the Data Watchpoint and Trace (DWT) unit. Chapter 10 Instrumentation Trace Macrocell Unit This chapter describes the Instrumentation Trace Macrocell (ITM) unit. Chapter 11 Trace Port Interface Unit This chapter describes the Cortex-M4 TPIU, the Trace Port Interface Unit that is specific to the Cortex-M4 processor. Appendix A Revisions The technical changes between released issues of this manual. Preface About this book ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 7 Non-Confidential
boo Glossary The ARM Glossary is a list of terms used in ARM documentation,together with definitions for those terms.The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning. See the ARMGlossary for more information. Typographic conventions italie Introduces special terminology,denotes cross-references,and citations. bold Highlight ce elements,such as menu names.Denotes signal names.Also used for terms list monospace Denotes text that you can enter at the keyboard,such as commands,file and program names, and source code. tted abb instead of the full command or option name. and or option.You can enter the underlined text monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value onosp language key ords when used outside example code <and> Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example MRC p15,0 <Rd>,<CRn>,<CRm>,<Opcode_2> SMALL CAPITALS Timing diagrams The following figure explains the components used in timing diagrams.Variations,when they occur. haveclear labels.You must not assume any timing information that is not explicit in the diagrams. Shade Clock☐ HIGH to LOW Transient HIGHLOW to HIGH Bus stable Busto high impedance Bus change High impedance to stable bus Figure 1 Key to timing diagram conventions Signals The signal conventions are ARM100166_0001_00_en 8
Glossary The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning. See the ARM Glossary for more information. Typographic conventions italic Introduces special terminology, denotes cross-references, and citations. bold Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate. monospace Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. monospace Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value. monospace bold Denotes language keywords when used outside example code. <and> Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example: MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2> SMALL CAPITALS Used in body text for a few terms that have specific technical meanings, that are defined in the ARM glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE. Timing diagrams The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams. Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation. Clock HIGH to LOW Transient HIGH/LOW to HIGH Bus stable Bus to high impedance Bus change High impedance to stable bus Figure 1 Key to timing diagram conventions Signals The signal conventions are: Preface About this book ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 8 Non-Confidential
About thisbook Signal level The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means .HIGH for active-HIGH signals. LOW for active-LOW signals. hered ofme denoe Lower-case Additional reading This book contains information that is specific to this product.See the following documents for other relevant information. 7-MArchicre Reference Ma(ARM) M4 and Imp ARM DII 0239) Re HB-I v1.0)(A RM AMBA3 APB Protocol on (ARM IHI ence Ma ARM DDI0314) ARM D ication (ARM H00 Cortex-M4 Lay Stacking and Context Switehing Application Note 29 (ARM DA10298). Other publications IEEE Standard [Test Access Port and Boundary-Scan Architecture 1149.1-2001 (JTAG) .IEEE Standard [EEE Standard for Binary Floating-Point Arithmetic]754-2008. ARM100166000100en opygh1ghtsv 9
Signal level The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means: • HIGH for active-HIGH signals. • LOW for active-LOW signals. Lower-case n At the start or end of a signal name denotes an active-LOW signal. Additional reading This book contains information that is specific to this product. See the following documents for other relevant information. ARM publications • ARMv7-M Architecture Reference Manual (ARM DDI 0403). • ARM® Cortex-M4 Integration and Implementation Manual (ARM DII 0239). • ARM ETM-M4 Technical Reference Manual (ARM DDI 0440). • ARM AMBA® 3 AHB-Lite Protocol (v1.0) (ARM IHI 0033). • ARM AMBA 3 APB Protocol Specification (ARM IHI 0024). • ARM CoreSight™ Components Technical Reference Manual (ARM DDI 0314). • ARM Debug Interface v5 Architecture Specification (ARM IHI 0031). • Cortex-M4 Lazy Stacking and Context Switching Application Note 298 (ARM DAI0298). Other publications • IEEE Standard [Test Access Port and Boundary-Scan Architecture ]1149.1-2001 (JTAG). • IEEE Standard [IEEE Standard for Binary Floating-Point Arithmetic] 754-2008. Preface About this book ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 9 Non-Confidential
Pc Feedback Feedback on this product If you have any commentsor sugestions about this product.contact your suppler and give The product name. The product revision or version An expla ation with as much information as you can provide.Include symptoms and diagnostic procedures if appropriate Feedback on content If you have comments on content then send an e-mail toerrrcmGive: The titl The number ARM 100166_0001_00_en. The page number(s)to which your comments refer A concise explanation of your comments. ARMalso welcomes general suggestions for additions and improvements Note ARM100166_0001_00_en coapy7gne20o9,2010,2018305AdMAWngses9ned 10
Feedback Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • The product name. • The product revision or version. • An explanation with as much information as you can provide. Include symptoms and diagnostic procedures if appropriate. Feedback on content If you have comments on content then send an e-mail to errata@arm.com. Give: • The title. • The number ARM 100166_0001_00_en. • The page number(s) to which your comments refer. • A concise explanation of your comments. ARM also welcomes general suggestions for additions and improvements. Note ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. Preface Feedback ARM 100166_0001_00_en Copyright © 2009, 2010, 2013, 2015 ARM. All rights reserved. 10 Non-Confidential