专题一SOC设计方法学
专题一 SOC设计方法学
片上系统S0C的优势 高性能 低功耗 体积小 重量轻 成本低
片上系统SOC的优势 高性能 低功耗 体积小 重量轻 成本低
S0C对EDA技术的挑战 SOC可集成: processors, embedded memories, programmable logic, and various application-specific circuit components designed by multiple teams for multiple projects ·芯片规模呈指数增长 设计复杂性呈指数增长 设计领域中挑战与机会并存
SOC对EDA技术的挑战 • SOC可集成： processors, embedded memories, programmable logic, and various application-specific circuit components designed by multiple teams for multiple projects. • 芯片规模呈指数增长 • 设计复杂性呈指数增长 • 设计领域中挑战与机会并存
设计复杂性星双指数倍增长 C1: complexity due to exponential increase of chip capacity More devices More power Heterogeneous integration C2: complexity due to exponential decrease of feature size Interconnect delay Coupling noise EMI(Electro Magnetic Interference) Design Complexity oc Cl C2
设计复杂性呈双指数倍增长 • C1: complexity due to exponential increase of chip capacity ---- More devices ---- More power ---- Heterogeneous integration • C2: complexity due to exponential decrease of feature size ---- Interconnect delay ---- Coupling noise ---- EMI(Electro Magnetic Interference) • Design Complexity C1 x C2
Productivity Gap Chip Capacity and Designer Productivity 10000000 100000000 1000000 10000000 10000 58%Yr Complexity 1000000 10000 growth rate 100000 1000 10000 100 BnY. 1000 Productiv ity growth rate 100 1982 1990 2000 2010
Productivity Gap Chip Capacity and Designer Productivity Logic Transistors/Chip(K) Transistors/Staff-Month 1 10 100 1000 10000 100000 1000000 10000000 10 100 1000 10000 100000 1000000 10000000 100000000 2010 1982 1990 2000 58%/Yr. Complexity growth rate 21%/Yr. Productivity growth rate