always实现组合逻辑：4选1数据选择器ALISTOTONGmodule mux4_1(out,in0,in1,in2,in3,sel)output out;input ino,in1,in2,in3;input[1:0] sel;reg out;always @(in0 or in1 or in2 or in3 or sel)case(sel)2'b00:out=inO;2'b01:out=in1;2'b10:out=in2;2'b11:out=in3;default:out=2'bx;endcaseendmodule12ZUZOTZ3
2025/12/3 12 always实现组合逻辑： 4选1数据选择器 module mux4_1(out,in0,in1,in2,in3,sel); output out; input in0,in1,in2,in3; input[1:0] sel; reg out; always @(in0 or in1 or in2 or in3 or sel) case(sel) 2'b00: out=in0; 2'b01: out=in1; 2'b10: out=in2; 2'b11: out=in3; default: out=2'bx; endcase endmodule
敏感信号类型一致大Talways@(posedge clkorposedgeclr)OTONGalways@(A orB）always@(posedgeclkorclr)X132025/12/3
2025/12/3 13 敏感信号类型一致 ❖always@(posedge clk or posedge clr) ❖always@(A or B) ❖always@(posedge clk or clr) ×
posedge &negedgeXT同步置位、同步清零计数器OTONGmodulecount(out,data,load,reset,clk);output[7:o]out;input[7:0] data;inputload,clk,reset;reg[7:0] out;l/注意敏感信号为何没有resetload？always@(posedgeclk)beginif (lreset)out=8'h00;elseif(load)out=data;elseout=out+1;endendmodule2025/12/3
2025/12/3 14 posedge & negedge ❖同步置位、同步清零计数器 module count(out,data,load,reset,clk); output[7:0] out; input[7:0] data; input load,clk,reset; reg[7:0] out; always @(posedge clk) //注意敏感信号为何没有reset load？ begin if (!reset) out = 8'h00; else if (load) out = data; else out = out + 1; end endmodule
异步控制信号1909T心高电平有效OTONGalways@(posedgeclk or posedgeclear)心低电平有效always@(posedge clk ornegedge clear心内外一致152025/12/3
2025/12/3 15 异步控制信号 ❖高电平有效 ▪ always@(posedge clk or posedge clear) ❖低电平有效 ▪ always@(posedge clk or negedge clear) ❖内外一致
内外一致Talways@(posedge clkor negedge clearOTONGbeginif(clear)out=o;elseout=in;end162025/12/3
2025/12/3 16 内外一致 always@(posedge clk or negedge clear) begin if(clear) out=0; else out=in; end