eluding the ADC, not exceed the minimum acceptable level required to demodulate the weakest signal of interest. Clearly, third-order intermodulation distortion generated by"A"and"B"(2B-A, and 2A- B)will distort signals C and D if the nonlinearities in the front-end are severe Strong out-of-band signals can also introduce distortion; signal"E"in Figure 5. 11 shows a large signal that is partially attenuated by the antialiasing filter. In many systems, the power level of the individual transmitters is under control of the base station. This capability helps to reduce the total dynamic range required BROADBAND DIGITAL RECEIVER ADC INPUT AMPLITUDE BANDPASS RESPONSE D A B C Figure 5.11 In broadband receiver applications(using an rF frequency of approximately 900MHz, and a first-IF frequency of 70MHz), SFDR requirements for the aDC are typically 70 to 80dBc Signal bandwidths between 5MHz and 10MHz are common requiring corresponding sampling rates of 1oMSPS to 20MSPS Sampling ADCs are generally designed to process signals up to Nyquist (f/2)with a reasonable amount of dynamic performance. As we have seen, however, even though the input bandwidth of a sampling adC is usually much greater than its maximum sampling rate, the SFDR and effective bit (enoB)performance usually decreases dramatically for full scale input signals much above fs/2. This implies that the selection criteria for ADCs used in undersampling applications is SFDR or ENOB at the if frequency, rather than sampling rate The general procedure for selecting an AdC for an undersampling application is not straightforward. The signal bandwidth and its location within the frequency spectrum must be known. The bandwidth of the signal determines the minimum sampling rate required and in order to ease the requirement on the antialiasing filter, a sampling rate of 2.5 times the signal bandwidth works well. After determining the approximate sampling frequency needed select the adc based on the required SFDR, S/(N+D), or eNOB at the IF frequency. This is where the dilemma usually occurs. You will find that an ADC specified for a maximum sampling rate of 10MSPS, for instance, will not have adequate SFDR at the IF frequency(72 5MHz in the example above), even though its performance is excellent up to its Nyquist frequency of 5Mhz. In order to meet the SFDr, S/(N+D), or ENOB
1 1 including the ADC, not exceed the minimum acceptable level required to demodulate the weakest signal of interest. Clearly, third-order intermodulation distortion generated by "A" and "B" (2B - A, and 2A - B) will distort signals C and D if the nonlinearities in the front-end are severe. Strong out-of-band signals can also introduce distortion; signal "E" in Figure 5.11 shows a large signal that is partially attenuated by the antialiasing filter. In many systems, the power level of the individual transmitters is under control of the base station. This capability helps to reduce the total dynamic range required. BROADBAND DIGITAL RECEIVER ADC INPUT Figure 5.11 In broadband receiver applications (using an RF frequency of approximately 900MHz, and a first-IF frequency of 70MHz), SFDR requirements for the ADC are typically 70 to 80dBc. Signal bandwidths between 5MHz and 10MHz are common, requiring corresponding sampling rates of 10MSPS to 20MSPS. Sampling ADCs are generally designed to process signals up to Nyquist (fs /2) with a reasonable amount of dynamic performance. As we have seen, however, even though the input bandwidth of a sampling ADC is usually much greater than its maximum sampling rate, the SFDR and effective bit (ENOB) performance usually decreases dramatically for full scale input signals much above fs /2. This implies that the selection criteria for ADCs used in undersampling applications is SFDR or ENOB at the IF frequency, rather than sampling rate. The general procedure for selecting an ADC for an undersampling application is not straightforward. The signal bandwidth and its location within the frequency spectrum must be known. The bandwidth of the signal determines the minimum sampling rate required, and in order to ease the requirement on the antialiasing filter, a sampling rate of 2.5 times the signal bandwidth works well. After determining the approximate sampling frequency needed, select the ADC based on the required SFDR, S/(N+D), or ENOB at the IF frequency. This is where the dilemma usually occurs. You will find that an ADC specified for a maximum sampling rate of 10MSPS, for instance, will not have adequate SFDR at the IF frequency (72.5MHz in the example above), even though its performance is excellent up to its Nyquist frequency of 5Mhz. In order to meet the SFDR, S/(N+D), or ENOB
requirement, you will generally require an ADC having a much higher sampling rat than is actua lly needed Figure 5. 12 shows the approximate SFDR versus input frequency for the series of low distortion ADCs. Notice that the AD9042 has superior SFDR OMSPS AD9022/AD9023(20MSPS), AD9026/AD9027 31MSPS), and the AD9042(40 performance SEDR COMPARISON BETWEEN 12-BIT SAMPLING ADCs FOR (dBc) AD9042 D9026AD9027 INPUT FREQUENCY(MHz) Figure 5.12 The AD9042 is a state-of-the-art 12-bit, 40MSPS two stage subranging adc consisting of a 6-bit coarse ADC and a 7-bit residue adC with one bit of overlap to correct for any dNL, INL, gain or offset errors of the coarse ADC, and offset errors in the residue path. a block diagram is shown in Figure 5. 13. A proprietary gray. code architecture is used to implement the two internal ADCs. The gain alignment of the coarse and residue, likewise the subtraction Dac, rely on the statistical matching of the process. As a result, 12-bit integral and differential linearity is obtained without laser trim. The internal daC consists of 126 interdigitated current sources. Also on the dac reference are an additional 20 interdigitated current sources to set the coarse gain, residue gain, and full scale gain. The removes the requirement for laser trim. The AD9042 is fabricated on a high speed dielectrically isolated complementary bipolar process. The total power dissipation is only 575mW when operating on a single +5V supply
1 2 requirement, you will generally require an ADC having a much higher sampling rate than is actually needed. Figure 5.12 shows the approximate SFDR versus input frequency for the AD9022/AD9023 (20MSPS), AD9026/AD9027 (31MSPS), and the AD9042 (40MSPS) series of low distortion ADCs. Notice that the AD9042 has superior SFDR performance. SFDR COMPARISON BETWEEN 12-BIT SAMPLING ADCs Figure 5.12 The AD9042 is a state-of-the-art 12-bit, 40MSPS two stage subranging ADC consisting of a 6-bit coarse ADC and a 7-bit residue ADC with one bit of overlap to correct for any DNL, INL, gain or offset errors of the coarse ADC, and offset errors in the residue path. A block diagram is shown in Figure 5.13. A proprietary graycode architecture is used to implement the two internal ADCs. The gain alignments of the coarse and residue, likewise the subtraction DAC, rely on the statistical matching of the process. As a result, 12-bit integral and differential linearity is obtained without laser trim. The internal DAC consists of 126 interdigitated current sources. Also on the DAC reference are an additional 20 interdigitated current sources to set the coarse gain, residue gain, and full scale gain. The interdigitization removes the requirement for laser trim. The AD9042 is fabricated on a high speed dielectrically isolated complementary bipolar process. The total power dissipation is only 575mW when operating on a single +5V supply